Abstract: A voltage-mode digital-to-analog converter (DAC) includes multiple bit processing circuits to generate an output voltage responsive to a binary input. Each of the multiple bit processing circuits includes a first switch circuit and a second switch circuit. The first switch circuit is to selectively couple one of multiple reference voltages to a first output load in response to receiving a first input bit during a first bit time. The first output load has a value proportional to d. The second switch circuit is to selectively couple one of the multiple reference voltages to a second output load in response to receiving a second input bit during a second bit time. The second output load has a value corresponding to the first output load. The first and second output loads are disposed in parallel, and serially couple to a third output load having a value proportional to (1-d).

Abstract: A voltage-mode digital-to-analog converter (DAC) includes input circuitry and an array of output impedance units disposed in parallel. The input circuitry receives a digital word of N bits. A selectable number of the output impedance units are activated to produce a desired aggregate output impedance. The selectable number is free to be a number different than N.

Abstract: A digital-to-analog converter (DAC) includes input circuitry to receive a digital word of N bits, and an array of N bit processing units disposed in parallel. Each of the N bit processing units includes first switch circuitry to generate a first output state based on a first value of a received one of the N bits, and second switch circuitry to generate a second output state based on a second value of the received one of the N bits. The DAC also includes selectively enabled third switch circuitry to generate a conditional third output state. A voltage-mode driver includes input circuitry to selectively receive one of N bits of a digital word. First switch circuitry generates a first output state based on a first value of the received one of the N bits. Second switch circuitry generates a second output state based on a second value of the received one of the N bits. Selectively enabled third switch circuitry generates a conditional third output state.

Abstract: In a method to improve error reduction in a digital-to-analog converter (DAC), comprising a mapping matrix block and a plurality of selectable source units which supply signals that in combination provide for analog output signals, mapping input signals, obtained from digital input signals to be converted into the analog output signals, are supplied to the mapping matrix block. In the mapping matrix block mapping output signals are generated in response to said mapping input signals and to mapping control signals derived from errors occurring in the plurality of selectable source units. At least one of the mapping input signals is applied for the substantially simultaneous generation of the mapping output signals for a number of source units.

Abstract: A digital to analog converter including a first current source (3) to which a first digital signal (28,31) is applied for conversion to an analog signal, wherein the first digital signal has a predetermined clock cycle. The digital to analog converter further comprising a second dummy current source (30) associated with the first current source to which a second digital signal (29,32) is applied. The second digital signal is derived from the first digital signal so that in any one clock cycle either the first or the second current source switches. This arrangement has the advantage that the dynamic behavior of the converter is not signal dependent, but dependent only on the clock cycle.

Abstract: In a method to improve error reduction in a digital-to-analog converter (DAC), comprising a mapping matrix block and a plurality of selectable source units which supply signals that in combination provide for analog output signals, mapping input signals, obtained from digital input signals to be converted into the analog output signals, are supplied to the mapping matrix block. In the mapping matrix block mapping output signals are generated in response to said mapping input signals and to mapping control signals derived from errors occurring in the plurality of selectable source units. At least one of the mapping input signals is applied for the substantially simultaneous generation of the mapping output signals for a number of source units.

Abstract: A digital to analog converter including a first current source (3) to which a first digital signal (28,31) is applied for conversion to an analog signal, wherein the first digital signal has a predetermined clock cycle. The digital to analog converter further comprising a second dummy current source (30) associated with the first current source to which a second digital signal (29,32) is applied. The second digital signal is derived from the first digital signal so that in any one clock cycle either the first or the second current source switches. This arrangement has the advantage that the dynamic behavior of the converter is not signal dependent, but dependent only on the clock cycle.

Abstract: A digital to analog converter comprises a plurality of conversion elements as well as a reference conversion element and further comprises mismatch calibration unit for calibrating at least one of the conversion elements in response to a comparison of that element's output with the output of the reference conversion element. The mismatch calibration unit calibrates the source with respect to static and dynamic mismatch by determining under varying circumstances the difference between outputs from a conversion element and reference conversion element.