Abstract: A method to manage fast random access of a DRAM memory is described. The method includes steps of: dividing the memory into memory banks accessible independently in read and write mode; identifying the address of the bank concerned by a current request and comparing the address of the bank concerned by a current request with the addresses of the N?1 banks previously requested. N is an integral number of cycles necessary for executing a request. If the address of the bank concerned by a current request is equal to the address of a bank corresponding to one of the N?1 previous requests, then the method further includes steps of suspending and memorizing the current request until the previous request involving the same bank is executed, otherwise the current request is executed.

Abstract: A method of fast random access management of a DRAM-type memory, including the steps of: dividing the memory into memory banks accessible independently in read and write mode; identifying the address of the bank concerned by a current request; comparing the address of the bank concerned by a current request with the addresses of the N?1 banks previously required, N being an integral number of cycles necessary to the executing of a request; and if the address of the bank concerned by a current request is equal to the address of a bank corresponding to one of the N?1 previous requests, suspending and memorizing the current request until the previous request involving the same bank is executed, otherwise, executing it.

Abstract: The content of a few pages of the dynamic random access memory is backed up, then one tries to refresh them less quickly, for example two times less quickly, and one observes whether this does or does not cause errors. The operation is repeated on the entire memory. Depending on the number of errors that have appeared on the pages refreshed less often, the refresh period is decreased or increased. Thus, the memory self-adjusts its refresh period to what is necessary for it.

Abstract: The content of a few pages of the dynamic random access memory is backed up, then one tries to refresh them less quickly, for example two times less quickly, and one observes whether this does or does not cause errors. The operation is repeated on the entire memory. Depending on the number of errors that have appeared on the pages refreshed less often, the refresh period is decreased or increased. Thus, the memory self-adjusts its refresh period to what is necessary for it.

Abstract: A method of fast random access management of a DRAM-type memory, including the steps of: dividing the memory into memory banks accessible independently in read and write mode; identifying the address of the bank concerned by a current request; comparing the address of the bank concerned by a current request with the addresses of the N−1 banks previously required, N being an integral number of cycles necessary to the executing of a request; and if the address of the bank concerned by a current request is equal to the address of a bank corresponding to one of the N−1 previous requests, suspending and memorizing the current request until the previous request involving the same bank is executed, otherwise, executing it.

Abstract: A method of fast random access management of a DRAM-type memory, including the steps of: dividing the memory into memory banks accessible independently in read and write mode; identifying the address of the bank concerned by a current request; comparing the address of the bank concerned by a current request with the addresses of the N−1 banks previously required, N being an integral number of cycles necessary to the executing of a request; and if the address of the bank concerned by a current request is equal to the address of a bank corresponding to one of the N−1 previous requests, suspending and memorizing the current request until the previous request involving the same bank is executed, otherwise, executing it.

Abstract: This invention relates to a circuit for calculating a syndrome on packets of n p-bit data, including a syndrome `register receiving the sum of each received datum and of the contents of the syndrome register modified by a first interconnection matrix corresponding to the p-th power of a generator polynomial. Each received datum defines a new packet of n data and the above-mentioned sum includes the datum preceding the new packet, modified by a second interconnection matrix corresponding to the n-th power of the first matrix.