Patents by Inventor Joseph C. Circello

Joseph C. Circello has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10360162
    Abstract: Embodiments include processing systems that determine, based on an instruction address range indicator stored in a first register, whether a next instruction fetch address corresponds to a location within a first memory region associated with a current privilege state or within a second memory region associated with a different privilege state. When the next instruction fetch address is not within the first memory region, the next instruction is allowed to be fetched only when a transition to the different privilege state is legal. In a further embodiment, when a data access address is generated for an instruction, a determination is made, based on a data address range indicator stored in a second register, whether access to a memory location corresponding to the data access address is allowed. The access is allowed when the current privilege state is a privilege state in which access to the memory location is allowed.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: July 23, 2019
    Assignee: NXP USA, Inc.
    Inventors: Daniel M. McCarthy, Joseph C. Circello, Kristen A. Hausman
  • Patent number: 10210040
    Abstract: Multi-dimensional parity checker (MDPC) systems and related methods are disclosed to check parity of data regions within external memories. In one embodiment, the MDPC system includes a control register and a parity checker. The parity checker receives data segments accessed from the data region. The parity checker generates and accumulates multi-dimensional parity bits for the data segments and subsequently compares accumulated bits to expected multi-dimensional parity bits to generate multi-dimensional error syndrome bits representing identified comparison errors. The parity checker also determines a syndrome state based upon the multi-dimensional syndrome bits and stores the syndrome state within the control register. The parity checker operates in different modes based upon different values stored in an operational mode field of the control register.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: February 19, 2019
    Assignee: NXP USA, Inc.
    Inventors: Joseph C. Circello, David J. Schimke
  • Patent number: 10073797
    Abstract: A processor begins exception processing in response to an exception event. Exception processing by the processor is halted during exception processing to facilitate debugging. The exception event can be a reset exception event or an interrupt exception event. Normal exception processing by the data processor can be resumed after debugging, or exception processing by the data processor can be aborted to allow the normal execution of instructions by the data processor to resume. An exception event can be selectively treated as an interrupt or a reset.
    Type: Grant
    Filed: February 22, 2008
    Date of Patent: September 11, 2018
    Assignee: NXP USA, Inc.
    Inventors: Joseph C. Circello, Ujwala R. Malwade, Daniel M. McCarthy
  • Publication number: 20180075258
    Abstract: A master domain assignment controller includes a first plurality of registers corresponding to a first processor including a first register corresponding to a first set of process identifiers (PIDs) and a second register corresponding to a second set of PIDs, and comparison circuitry. The comparison circuitry is coupled to receive an input PID from the first processor and is configured to determine if the input PID is one of the first set or the second set of PIDs. When the input PID is one of the first set of PIDs, a first output domain identifier (DID) is generated, and when the input PID is one of the second set of PIDs, a second output DID different from the first output DID is generated.
    Type: Application
    Filed: September 14, 2016
    Publication date: March 15, 2018
    Inventors: Joseph C. CIRCELLO, Michael E. LUNDAHL
  • Patent number: 9824242
    Abstract: A storage location of a device that can be configured to act as a master in a particular security mode, such as a Direct Memory Access (DMA) having one or more channels, can be programmed to indicate a security indicator to be provided when configured to operate as a master device.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: November 21, 2017
    Assignee: NXP USA, INC.
    Inventors: Joseph C. Circello, Daniel M. McCarthy, John D. Mitchell, Peter J. Wilson, John J. Vaglica
  • Publication number: 20170242803
    Abstract: Embodiments include processing systems that determine, based on an instruction address range indicator stored in a first register, whether a next instruction fetch address corresponds to a location within a first memory region associated with a current privilege state or within a second memory region associated with a different privilege state. When the next instruction fetch address is not within the first memory region, the next instruction is allowed to be fetched only when a transition to the different privilege state is legal. In a further embodiment, when a data access address is generated for an instruction, a determination is made, based on a data address range indicator stored in a second register, whether access to a memory location corresponding to the data access address is allowed. The access is allowed when the current privilege state is a privilege state in which access to the memory location is allowed.
    Type: Application
    Filed: May 3, 2017
    Publication date: August 24, 2017
    Inventors: Daniel M. McCarthy, Joseph C. Circello, Kristen A. Hausman
  • Patent number: 9729319
    Abstract: Methods and systems are disclosed for key management for on-the-fly hardware decryption within an integrated circuit. Encrypted information is received from an external memory and stored in an input buffer within the integrated circuit. The encrypted information includes one or more encrypted key blobs. The encrypted key blobs include one or more secret keys for encrypted code associated with one or more encrypted software images stored within the external memory. A key-encryption key (KEK) code for the encrypted key blobs is received from an internal data storage medium within the integrated circuit, and the KEK code is used to generate one or more key-encryption keys (KEKs). A decryption system then decrypts the encrypted key blobs using the KEKs to obtain the secret keys, and the decryption system decrypts the encrypted code using the secret keys. The resulting decrypted software code is then available for further processing.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: August 8, 2017
    Assignee: NXP USA, Inc.
    Inventors: Joseph C. Circello, David J. Schimke, Mohit Arora, Lawrence L. Case, Rodney D. Ziolkowski
  • Publication number: 20170220414
    Abstract: Multi-dimensional parity checker (MDPC) systems and related methods are disclosed to check parity of data regions within external memories. In one embodiment, the MDPC system includes a control register and a parity checker. The parity checker receives data segments accessed from the data region. The parity checker generates and accumulates multi-dimensional parity bits for the data segments and subsequently compares accumulated bits to expected multi-dimensional parity bits to generate multi-dimensional error syndrome bits representing identified comparison errors. The parity checker also determines a syndrome state based upon the multi-dimensional syndrome bits and stores the syndrome state within the control register. The parity checker operates in different modes based upon different values stored in an operational mode field of the control register.
    Type: Application
    Filed: January 28, 2016
    Publication date: August 3, 2017
    Inventors: Joseph C. Circello, David J. Schimke
  • Patent number: 9672164
    Abstract: Embodiments include processing systems that determine, based on an instruction address range indicator stored in a first register, whether a next instruction fetch address corresponds to a location within a first memory region associated with a current privilege state or within a second memory region associated with a different privilege state. When the next instruction fetch address is not within the first memory region, the next instruction is allowed to be fetched only when a transition to the different privilege state is legal. In a further embodiment, when a data access address is generated for an instruction, a determination is made, based on a data address range indicator stored in a second register, whether access to a memory location corresponding to the data access address is allowed. The access is allowed when the current privilege state is a privilege state in which access to the memory location is allowed.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: June 6, 2017
    Assignee: NXP USA, INC.
    Inventors: Daniel M. McCarthy, Joseph C. Circello, Kristen A. Hausman
  • Patent number: 9489316
    Abstract: Access requests to access data operands from memory space designated as a type of execute-only memory are allowed to precede in response to determining that the operand access request was generated using a particular type of addressing mode.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: November 8, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Joseph C. Circello, Daniel M. McCarthy, David J. Schimke
  • Patent number: 9418246
    Abstract: Methods and systems are disclosed for on-the-fly decryption within an integrated circuit that adds zero additional cycles of latency within the overall decryption system performance. A decryption system within a processing system integrated circuit generates an encrypted counter value using an address while encrypted code associated with an encrypted software image is being obtained from an external memory using the address. The decryption system then uses the encrypted counter value to decrypt the encrypted code and to output decrypted code that can be further processed. A secret key and an encryption engine can be used to generate the encrypted counter value, and an exclusive-OR logic block can process the encrypted counter value and the encrypted code to generate the decrypted code. By pre-generating the encrypted counter value, additional cycle latency is avoided. Other similar data independent encryption/decryption techniques can also be used such as output feedback encryption/decryption modes.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: August 16, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Joseph C. Circello, David J. Schimke, Mohit Arora, Lawrence L. Case, Rodney D. Ziolkowski
  • Publication number: 20160171249
    Abstract: Methods and systems are disclosed for on-the-fly decryption within an integrated circuit that adds zero additional cycles of latency within the overall decryption system performance. A decryption system within a processing system integrated circuit generates an encrypted counter value using an address while encrypted code associated with an encrypted software image is being obtained from an external memory using the address. The decryption system then uses the encrypted counter value to decrypt the encrypted code and to output decrypted code that can be further processed. A secret key and an encryption engine can be used to generate the encrypted counter value, and an exclusive-OR logic block can process the encrypted counter value and the encrypted code to generate the decrypted code. By pre-generating the encrypted counter value, additional cycle latency is avoided. Other similar data independent encryption/decryption techniques can also be used such as output feedback encryption/decryption modes.
    Type: Application
    Filed: December 15, 2014
    Publication date: June 16, 2016
    Inventors: Joseph C. Circello, David J. Schimke, Mohit Arora, Lawrence L. Case, Rodney D. Ziolkowski
  • Publication number: 20160173282
    Abstract: Methods and systems are disclosed for key management for on-the-fly hardware decryption within an integrated circuit. Encrypted information is received from an external memory and stored in an input buffer within the integrated circuit. The encrypted information includes one or more encrypted key blobs. The encrypted key blobs include one or more secret keys for encrypted code associated with one or more encrypted software images stored within the external memory. A key-encryption key (KEK) code for the encrypted key blobs is received from an internal data storage medium within the integrated circuit, and the KEK code is used to generate one or more key-encryption keys (KEKs). A decryption system then decrypts the encrypted key blobs using the KEKs to obtain the secret keys, and the decryption system decrypts the encrypted code using the secret keys. The resulting decrypted software code is then available for further processing.
    Type: Application
    Filed: December 15, 2014
    Publication date: June 16, 2016
    Inventors: Joseph C. Circello, David J. Schimke, Mohit Arora, Lawrence L. Case, Rodney D. Ziolkowski
  • Publication number: 20150332069
    Abstract: A storage location of a device that can be configured to act as a master in a particular security mode, such as a Direct Memory Access (DMA) having one or more channels, can be programmed to indicate a security indicator to be provided when configured to operate as a master device.
    Type: Application
    Filed: July 27, 2015
    Publication date: November 19, 2015
    Inventors: Joseph C. Circello, Daniel M. McCarthy, John D. Mitchell, Peter J. Wilson, John J. Vaglica
  • Patent number: 9116845
    Abstract: A system and method are disclosed for determining whether to allow or deny an access request based upon one or more descriptors at a local memory protection unit and based upon one or more descriptors a system memory protection unit. When multiple descriptors of a memory protection unit apply to a particular request, the least-restrictive descriptor will be selected. System access information is stored at a cache of a local core in response to a cache line being filled. The cached system access information is merged with local access information, wherein the most-restrictive access is selected.
    Type: Grant
    Filed: February 23, 2011
    Date of Patent: August 25, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: William C. Moyer, Joseph C. Circello
  • Patent number: 9092647
    Abstract: A storage location of a device that can be configured to act as a master in a particular security mode, such as a Direct Memory Access (DMA) having one or more channels, can be programmed to indicate a security indicator to be provided when configured to operate as a master device.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: July 28, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Joseph C. Circello, Daniel M. McCarthy, John D. Mitchell, Peter J. Wilson, John J. Vaglica
  • Patent number: 8977790
    Abstract: An embodiment of an electronic system includes a processing element, a bus controller, and a peripheral module. The processing element executes machine readable code for performing a data transfer of an x-bit wide data value between the processing element and the peripheral module. Performing the data transfer includes providing a processing element-provided address corresponding to a y-bit wide data register of the peripheral module, where y is less than x. The bus controller receives the processing element-provided address, and in response, performs a series of multiple data transfers with the peripheral module. This includes providing a first peripheral address for a first data transfer of the series, and providing at least one different peripheral address for at least one other data transfer of the series. The peripheral module maps the first peripheral address and the at least one different peripheral address to the y-bit wide data register.
    Type: Grant
    Filed: February 15, 2008
    Date of Patent: March 10, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Joseph C. Circello
  • Publication number: 20140281137
    Abstract: Access requests to access data operands from memory space designated as a type of execute-only memory are allowed to precede in response to determining that the operand access request was generated using a particular type of addressing mode.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Inventors: Joseph C. Circello, Daniel M. McCarthy, David J. Schimke
  • Publication number: 20140259149
    Abstract: A storage location of a device that can be configured to act as a master in a particular security mode, such as a Direct Memory Access (DMA) having one or more channels, can be programmed to indicate a security indicator to be provided when configured to operate as a master device.
    Type: Application
    Filed: March 7, 2013
    Publication date: September 11, 2014
    Inventors: Joseph C. Circello, Daniel M. McCarthy, John D. Mitchell, Peter J. Wilson, John J. Vaglica
  • Publication number: 20130326193
    Abstract: Embodiments include processing systems that determine, based on an instruction address range indicator stored in a first register, whether a next instruction fetch address corresponds to a location within a first memory region associated with a current privilege state or within a second memory region associated with a different privilege state. When the next instruction fetch address is not within the first memory region, the next instruction is allowed to be fetched only when a transition to the different privilege state is legal. In a further embodiment, when a data access address is generated for an instruction, a determination is made, based on a data address range indicator stored in a second register, whether access to a memory location corresponding to the data access address is allowed. The access is allowed when the current privilege state is a privilege state in which access to the memory location is allowed.
    Type: Application
    Filed: May 31, 2012
    Publication date: December 5, 2013
    Inventors: DANIEL M. MCCARTHY, Joseph C. Circello, Kristen A. Hausman