Patents by Inventor Joseph C. Decuir

Joseph C. Decuir has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5781028
    Abstract: A bidirectional universal serial bus (USB) includes switched terminations that are selectively activated to terminate the receiving end of the data bus in its characteristic impedance. The USB includes a twisted pair data cable that permits bidirectional data communication between a USB interface in a computer and a USB peripheral device. To control the bidirectional communication, the USB defines a transmit mode and a receive mode. Each end of the twisted pair data cable includes a selectively activatable switch termination that terminates the twisted pair data cable in its characteristic impedance when selectively activated. When the USB peripheral device is in the receive mode, the switched termination within the USB peripheral device is selectively activated so that the twisted pair data cable is terminated in its characteristic impedance. This reduces ringing and electromagnetic (EM) radiation on the twisted pair data cable.
    Type: Grant
    Filed: June 21, 1996
    Date of Patent: July 14, 1998
    Assignee: Microsoft Corporation
    Inventor: Joseph C. Decuir
  • Patent number: 5594473
    Abstract: A computer that provides data to a video display using a bitmap display memory organization and bitplane addressing. Separate control is provided for two bitplane backgrounds and for eight reusable and easily movable sprites. Additional logic allows for dynamically-controllable interobject priority and collision detection among data in each of the bitplane backgrounds and sprites. A coprocessor provides for video beam-synchronized changes to data in registers, freeing the main processor for general purpose computing tasks. A block image transferer is provided to rapidly copy data in large blocks from one memory location to another. In hold-and-modify mode, color output circuitry holds the values for a previously displayed pixel while bitplane data modifies those values, allowing for simultaneous display of a greatly increased number of colors.
    Type: Grant
    Filed: March 8, 1993
    Date of Patent: January 14, 1997
    Assignee: Escom AG
    Inventors: Jay G. Miner, Dave Dean, Joseph C. Decuir, Ronald H. Nicholson, Akio Tanaka
  • Patent number: 4874164
    Abstract: A computer that provides data to a video display using a bitmap display memory organization and bitplane addressing. Separate control is provided for two bitplane backgrounds and for eight reusable and easily movable sprites. Additional logic allows for dynamically-controllable interobject priority and collision detection among data in each of the bitplane backgrounds and sprites. A coprocessor provides for video beam-synchronized changes to data in registers, freeing the main processor for general purpose computing tasks. A block image transfer is provided to rapidly copy data in large blocks from one memory location to another. In hold-and-modify mode, color output circuitry holds the value for a previously displayed pixel while bitplane data modifies those values, allowing for simultaneous display of a greatly increased number of colors.
    Type: Grant
    Filed: July 18, 1986
    Date of Patent: October 17, 1989
    Assignee: Commodore-Amiga, Inc.
    Inventors: Jay G. Miner, Dave Dean, Joseph C. Decuir, Ronald H. Nicholson, Akio Tanaka
  • Patent number: 4777621
    Abstract: A video game home computer is implemented in NMOS (n type metal oxide semiconductor) technology with plural microprocessors. Centralized bus architecture and direct memory access (DMA) techniques are employed. A video display generator provides color signal outputs to drive a commercial television receiver display. This display generator receives inputs from both microprocessors and obtains data directly from memory. A bit map of display information is kept in memory, wherein bits of information in memory image the precise screen display for each instance in time. A bit map manipulator circuit performs, under microprocessor direction, logic function manipulation of the bit map data. Access between system components is accomplished via the bus architecture on a priority queue basis. Chip count and chip area is minimized.
    Type: Grant
    Filed: July 19, 1985
    Date of Patent: October 11, 1988
    Assignee: Commodore-Amiga, Inc.
    Inventors: Jay G. Miner, Joseph C. Decuir, Ronald H. Nicholson
  • Patent number: 4471464
    Abstract: A microprocessor based data processing system including a microprocessor, a memory unit, and a display unit is provided with a programmable graphics generator that transfers graphics information from the memory unit to the display unit in response to and control of a set of display instructions also stored in the memory unit. The graphics generator includes a first addressing unit for sequentially accessing the display instructions from the memory unit; a control unit for receiving, storing and decoding such instruction and for issuing supervisory and control signals in response to the binary state of each instruction; a second addressing unit for accessing graphics information from the memory unit in response to the supervisory signals from the control unit; and a third addressing unit for accessing movable object graphics stored in the memory unit.
    Type: Grant
    Filed: April 29, 1983
    Date of Patent: September 11, 1984
    Assignee: Atari, Inc.
    Inventors: Steven T. Mayer, Jay G. Miner, Douglas G. Neubauer, Joseph C. Decuir
  • Patent number: 4471463
    Abstract: A microprocessor based data processing system including a microprocessor, a memory unit, and a display unit is provided with a programmable graphics generator that transfers graphics information from the memory unit to the display unit in response to and control of a set of display instructions also stored in the memory unit. The graphics generator includes a first addressing unit for sequentially accessing the display instructions from the memory unit; a control unit for receiving, storing and decoding such instruction and for issuing supervisory and control signals in response to the binary state of each instruction; a second addressing unit for accessing graphics information from the memory unit in response to the supervisory signals from the control unit; and a third addressing unit for accessing movable object graphics stored in the memory unit.
    Type: Grant
    Filed: April 22, 1983
    Date of Patent: September 11, 1984
    Assignee: Atari, Inc.
    Inventors: Steven T. Mayer, Jay G. Miner, Douglas G. Neubauer, Joseph C. Decuir
  • Patent number: 4471465
    Abstract: A microprocessor based data processing system including a microprocessor, a memory unit, and a display unit is provided with a programmable graphics generator that transfers graphics information from the memory unit to the display unit in response to and control of a set of display instructions also stored in the memory unit. The graphics generator includes a first addressing unit for sequentially accessing the display instructions from the memory unit; a control unit for receiving, storing and decoding such instruction and for issuing supervisory and control signals in response to the binary state of each instruction; a second addressing unit for accessing graphics information from the memory unit in response to the supervisory signals from the control unit; and a third addressing unit for accessing movable object graphics stored in the memory unit.
    Type: Grant
    Filed: May 16, 1983
    Date of Patent: September 11, 1984
    Assignee: Atari, Inc.
    Inventors: Steven T. Mayer, Jay G. Miner, Douglas G. Neubauer, Joseph C. Decuir
  • Patent number: 4435779
    Abstract: A microprocessor based data processing system including a microprocessor, a memory unit, and a display unit is provided with a programmable graphics generator that transfers graphics information from the memory unit to the display unit in response to and control of a set of display instructions also stored in the memory unit. The graphics generator includes a first addressing unit for sequentially accessing the display instructions from the memory unit; a control unit for receiving, storing and decoding such instruction and for issuing supervisory and control signals in response to the binary state of each instruction; a second addressing unit for accessing graphics information from the memory unit in response to the supervisory signals from the control unit; and a third addressing unit for accessing movable object graphics stored in the memory unit.
    Type: Grant
    Filed: June 8, 1981
    Date of Patent: March 6, 1984
    Assignee: Atari, Inc.
    Inventors: Steven T. Mayer, Jay G. Miner, Douglas G. Neubauer, Joseph C. Decuir
  • Patent number: 4296476
    Abstract: A microprocessor based data processing system including a microprocessor, a memory unit, and display unit is provided with a programmable graphics generator that transfers graphics information from the memory unit to the display unit in response to and control of a set of display instructions also stored in the memory unit. The graphics generator includes a first addressing unit for sequentially accessing the display instructions from the memory unit; a control unit for receiving, storing and decoding such instruction and for issuing supervisory and control signals in response to the binary state of each instruction; a second addressing unit for accessing graphics information from the memory unit in response to the supervisory signals from the control unit; and a third addressing unit for accessing movable object graphics stored in the memory unit.
    Type: Grant
    Filed: January 8, 1979
    Date of Patent: October 20, 1981
    Assignee: Atari, Inc.
    Inventors: Steven T. Mayer, Jay G. Miner, Douglas G. Neubauer, Joseph C. Decuir