Abstract: A switch for transferring UBR traffic on an ATM network. The switch includes a mechanism for receiving UBR traffic from the network and sending UBR traffic to the network. The switch includes a mechanism for prohibiting a predefined condition in the UBR traffic, the prohibiting mechanism connected to the receiving and sending mechanism. Alternatively, the switch includes a mechanism for receiving UBR traffic in connections from the network and sending UBR traffic in the connections to the network. The switch includes a mechanism for dynamic analysis of the connections of UBR traffic to determine whether the connections have UBR traffic which behaves or which misbehaves. Alternatively, the switch includes a mechanism for receiving UBR traffic in connections from the network and sending UBR traffic in the connections to the network. The switch includes a mechanism for reevaluating connections to determine whether the connections have UBR traffic which behaves or which misbehaves at a predetermined interval.

Abstract: A switching system. The switching system includes a first switch having a primary receive port and a secondary receive port. The switching system includes a second switch connected to the first switch. The second switch has n receive ports, where n is greater than or equal to 2 and is an integer. The second switch has m transmit ports, where m is greater than or equal to 2 and is an integer. The transmit ports are decoupled from the receive ports. The second switch has a connecting mechanism that includes a multicast mechanism which sends data out a primary transmit port of the m transmit ports to the primary receive port of the first switch to define a primary path, and out a secondary transmit port of the m transmit ports to a secondary receive port of the first switch to define a redundant path to the primary path so that if there is a failure of the primary path to provide the data to the first switch, the data is received by the first switch through the redundant path.

Abstract: A switch for switching traffic from N sources to M destinations, where M and N are each an integer greater than or equal to 2. The switch includes K segments, where K is greater than or equal to 2 and is an integer. Each segment receiving traffic from R of the N sources, where 1≦R<N and is an integer, and all K segments in total receiving traffic from the N sources. Each segment collecting and queuing traffic from the respective R sources. The switch includes an arbitrator which receives information from the destinations regarding if they can receive data or not, and from the K segments about the traffic they have for different destinations. A method for switching traffic from N sources to M destinations, where M and N are each an integer greater than or equal to 2. The method includes the steps of receiving traffic from the N sources at input ports of K segments, where K is greater than or equal to 2 and is an integer.

Abstract: A switch for switching fixed size ATM cells and variable length packets of a network. The switch includes an input port mechanism having a plurality of input ports each able to receive cells and packets from the network. The switch includes an output port mechanism having a plurality of output ports each able to send cells and packets to the network. The switch includes a switching fabric connected to the input port mechanism and the output port mechanism for switching either packets or cells from any input port to any output port. The switch includes a mechanism for converting packets to cells when the input port is a packet port and the output port is a cell port and cells to packets when the input port is a cell port and the output port is a packet port, respectively, or not converting cells or packets when the input port and the output port are both cell ports or both packet ports, respectively. The converting mechanism is connected to the output port mechanism and the switching fabric.

Abstract: A switch for an ATM communication system. The ATM communication system has an ATM network on which ATM cells travel, source nodes connected to the ATM network which produce ATM cells and send them onto the ATM network, and destination nodes connected to the ATM network which receive ATM cells from the ATM network. The switch comprises input ports through which cells are received from the ATM network. The switch comprises output ports through which cells are transmitted to the ATM network. The switch comprises a switching mechanism connected to the input ports and output ports which transfer cells from the input ports to output ports. The switching mechanism has a unicast sending mechanism for sending unicast cells to an output port and has a multicast sending mechanism for sending multicast cells to a desired output port. The multicast sending mechanism is separate and different from the unicast sending mechanism.

Abstract: An efficient polling technique to attain improved system performance preserves the concept of polling, but instead of polling across system buses to the device, a poll is made within the processor's cache structure, which is typically internal to the processor complex or attached on a local isolated bus. The polling status location is mapped in the cachable address space of the processor. Hence, the polling occurs to a normal cachable location. When the device completes its task, it signals to the polling loop by invalidating the cache line corresponding to the poll location. The next time software tries to read the status value, the processor misses in its cache and automatically reloads the updated status value from the device. This causes the polling loop to exit and normal processing continues. The only bus traffic that results is that which is issued by the device to signal cache line invalidation and a subsequent processor initiated cache line reload.

Abstract: In a graphics subsystem, a highly interactive two-dimensional (2D) data stream and a computationally intensive three-dimensional (3D) data stream are processed concurrently in such a manner that processing of the 2D data stream is not held up by processing of the 3D data stream. A 3D geometry subsystem having a parallel pipeline architecture is used to process the 3D data stream, while a 2D subsystem concurrently processed the 2D data stream in parallel with the 3D subsystem. A reordering device couples the processed 2D and 3D data streams to a common raster subsystem. The reordering device, which contains an internal buffer, reorders any order-dependent elements of the 3D data stream appearing at the output of the 3D geometry subsystem in an order different from the order in which they were supplied to the input end.