Patents by Inventor Joseph C. Langston

Joseph C. Langston has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6051344
    Abstract: A photolithography method for creating very small line dimensions includes making a mask by exposing a mask blank through a reticle in a reduction photolithography exposure tool, at a reduction of N. The fabricated mask is then placed in a second photolithography exposure tool at a second reduction M, to expose a wafer substrate at a reduction of M. The resulting patterned substrate will have a critical dimension equaling the critical dimension of the original reticle, divided by the factor N times M. In this manner, very small size patterns can be created even though a larger pattern starting reticle is used.
    Type: Grant
    Filed: March 27, 1998
    Date of Patent: April 18, 2000
    Assignee: Intel Corporation
    Inventors: Joseph C. Langston, Patrick M. Troccolo
  • Patent number: 5688409
    Abstract: A new process and an improved process for fabricating device layers with ultrafine features. In one embodiment a device layer to be patterned is deposited above a substrate and a photoresist layer is deposited above that device layer. A reticle having a first transparent layer and a second opaque layer is used to pattern the photoresist layer. The reticle includes a first region with a first phase and a second region with a second phase such that the incident radiation is shifted when passing through the reticle. The second reticle layer is disposed above the first reticle layer and proximate to the location where the first region transitions to the second region of the first reticle layer. A stepper is used to expose the photoresist to radiation through the reticle. The critical dimensions of the device layer being patterned are controlled by adjusting the partial coherence of the stepper during exposure.
    Type: Grant
    Filed: June 21, 1996
    Date of Patent: November 18, 1997
    Assignee: Intel Corporation
    Inventors: Giang T. Dao, Joseph C. Langston
  • Patent number: 5503959
    Abstract: A method of forming a patterned resist layer on a semiconductor substrate is described. The substrate is coated with a resist layer and placed on a substrate stage within a projection printer. The projection printer includes a radiation source that emits a radiation wave having a predetermined wavelength, a lens having a predetermined numerical aperture, and a reticle having an opaque section and a transparent section. The projection printer has a resolution that is a function of the wavelength and the numerical aperture. The resist layer is exposed to a radiation pattern formed at the surface of the resist layer when the radiation wave passes through the reticle. The radiation pattern includes a radiative area lying beneath the transparent section and a substantially radiation-free area lying beneath the opaque section. All dimensions of the radiation pattern at the surface of the resist layer are no less than the resolution.
    Type: Grant
    Filed: April 13, 1993
    Date of Patent: April 2, 1996
    Assignee: Intel Corporation
    Inventor: Joseph C. Langston