Abstract: A method and apparatus for limiting switching oscillations on an ISDN line interface circuit may be accomplished by sensing the current provided to the primary winding of the line coupling transformer (14). When the primary current is in a first pre-determined range, a first control signal (64) is generated such that a first impedance is applied across the primary winding during a trailing edge of the transformer switching. When the primary current is within a second pre-determined range, a second control signal (66) is produced that causes a second impedance to be imposed across a primary winding during the trailing edge of the transformer switching.

Abstract: A line driver (10) includes a first p-channel FET (12) and two n-channel FETs (14-16), wherein one of the n-channel FETs functions as a blocking FET (16). The p-channel FET (12) is coupled to the supply voltage (26) and the blocking FET (16), while the other n-channel FET (14) is coupled to a supply return (28) and the blocking FET (16). An output (30) is provided between the n-channel FET (14) and the blocking FET (16), while inputs (20-22) are provided to the p-channel FET (12) and the n-channel FET (16). In operation, the inputs (20-22) are supplied to the FETs at a given rate such that either the p-channel or the n-channel FET is "on". To ensure a maximum output swing when the p-channel FET is on, the blocking FET (16) is sourced by a charge pump (18).

Abstract: A one-bit adder includes a carry stage and an adding stage and is constructed in a fast CMOS complementary pass transistor logic with complementary analog CMOS switches in the adding stage which consist of a PMOS and an NMOS transistor. The source of the PMOS transistor is connected with the drain of the NMOS transistor and the drain of the PMOS transistor is connected with the source of the NMOS transistor. The gate of the PMOS transistor receives inverted signals with respect to the gate of the NMOS transistor. Two partial output sum signals are generated by two of the switches which are connected with the input and with the output, respectively, of an inverter and the output sum signal of the adder is available at the output of the inverter.