Abstract: Intelligent services are provided in a storage network using intelligent service modules that can be cabled to a switch external to the switch chassis and yet be managed as part of the switch's logical domain. Data and management communications between the intelligent service module and the core switch are provided through a “soft-backplane” implemented using in-band communications through cabling attached between the switch and the intelligent service module rather than through hardwired backplane within the chassis. Management communications from management software is directed to the switch, which handles the management functions relating to the intelligent service module or forwards the management requests to the intelligent service module for processing.

Abstract: A computer system includes a processor capable of executing a plurality of N threads of instructions, N being an integer greater than one, with a set of global registers visible to each of the plurality of threads and a plurality of busy bit memory elements used to signal whether or not a register is in use by a thread. The processor includes logic to stall a read from global register if the thread reading the global register is a speculative thread and the busy bits for prior threads are set. The processor might also include a speculative load address memory, into which speculative loads from speculative threads are entered and logic to compare addresses for stores from nonspeculative threads with addressees in the speculative load address memory and invalidate speculative threads corresponding to the speculative load addresses stored in the speculative load address memory.

Abstract: Differential configuration update commands can be communicated and applied quickly and efficiently to active zone sets and zone set libraries, without requiring propagation of entire zone sets through a fabric of a SAN. Furthermore, the commands can be applied quickly to support dynamic configuration updates. Ordered differential configuration update commands can be applied to ordered zone set data structures to minimize update instruction communication requirements and optimize configuration update operations. In addition, differential configuration update commands can be applied to active zone set data structures (e.g., in an active zone set or a zone set library) to optimize configuration update operations.

Abstract: A computer system includes a processor capable of executing a plurality of N threads of instructions, N being an integer greater than one, with a set of global registers visible to each of the plurality of threads and a plurality of busy bit memory elements used to signal whether or not a register is in use by a thread. The processor includes logic to stall a read from global register if the thread reading the global register is a speculative thread and the busy bits for prior threads are set. The processor might also include a speculative load address memory, into which speculative loads from speculative threads are entered and logic to compare addresses for stores from nonspeculative threads with addressees in the speculative load address memory and invalidate speculative threads corresponding to the speculative load addresses stored in the speculative load address memory.

Abstract: A method and apparatus for scheduling instructions to provide adequate prefetch latency is disclosed during compilation of a program code in to a program. The prefetch scheduler component of the present invention selects a memory operation within the program code as a “martyr load” and removes the prefetch associated with the martyr load, if any. The prefetch scheduler takes advantage of the latency associated with the martyr load to schedule prefetches for memory operations which follow the martyr load. The prefetches are scheduled “behind” (i.e., prior to) the martyr load to allow the prefetches to complete before the associated memory operations are carried out. The prefetch schedule component continues this process throughout the program code to optimize prefetch scheduling and overall program operation.

Abstract: A memory cache method and apparatus with two memory execution pipelines, each having a translation lookaside buffer (TLB). Memory instructions are executed in the first pipeline (324) by searching a data cache (310) and a prefetch cache (320). A large data TLB (330) provides memory for storing address translations for the first pipeline (324) A second pipeline (328) executes memory instructions by accessing the prefetch cache (320). A second micro-TLB (340) is associated with the second pipeline (328). It is loaded in anticipation of data that will be referenced by the second pipeline (328). A history file (360) is also provided to retain information on previous instructions to aid in deciding when to prefetch data. Prefetch logic (370) determines when to prefetch data, and steering logic (380) routes certain instructions to the second pipeline (328) to increase system performance.

Abstract: A memory cache method and apparatus with two memory execution pipelines, each having a translation lookaside buffer (TLB). Memory instructions are executed in the first pipeline (324) by searching a data cache (310) and a prefetch cache (320). A large data TLB (330) provides memory for storing address translations for the first pipeline (324) A second pipeline (328) executes memory instructions by accessing the prefetch cache (320). A second micro-TLB (340) is associated with the second pipeline (328). It is loaded in anticipation of data that will be referenced by the second pipeline (328). A history file (360) is also provided to retain information on previous instructions to aid in deciding when to prefetch data. Prefetch logic (370) determines when to prefetch data, and steering logic (380) routes certain instructions to the second pipeline (328) to increase system performance.