Abstract: A method for performing multi-wire signaling encoding is provided in which a clock signal is encoded within symbol transitions. A sequence of data bits is converted into a plurality of m transition numbers. Each transition number is converted into a sequential number from a set of sequential numbers. The sequential number is converted into a raw symbol that can be transmitted over a plurality of differential drivers. The raw symbol is transmitted spread over a plurality of n wires, wherein the clock signal is effectively embedded in the transmission of raw symbols since the conversion from transition number into a sequential number guarantees that no two consecutive raw symbols are the same. The raw symbol is guaranteed to have a non-zero differential voltage across all pairs of the plurality of n wires.

Abstract: System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A sequence of data bits is converted into M transition numbers, which are then converted into a sequence of symbols. The sequence of symbols is transmitted received over N wires. A clock signal may be effectively embedded in the transmission of the sequence of symbols. Each of the sequence of symbols may be selected based on a corresponding one of the M transition numbers and a value of a preceding one of the sequence of symbols.

Abstract: System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A sequence of data bits is converted into M transition numbers, which are then converted into a sequence of symbols. The sequence of symbols is transmitted received over N wires. A clock signal may be effectively embedded in the transmission of the sequence of symbols. Each of the sequence of symbols may be selected based on a corresponding one of the M transition numbers and a value of a preceding one of the sequence of symbols.

Abstract: A termination network circuit for a differential signal transmitter comprises a plurality of n resistance elements and a plurality of differential signal drivers. A first end of each of the resistance elements is coupled at a common node, where n is an integer value and is the number of conductors used to transmit a plurality of differential signals. Each differential signal driver may include a positive terminal driver and a negative terminal driver. The positive terminal driver is coupled to a second end of a first resistance element while the negative terminal driver is coupled to a second end of a second resistance element. The positive terminal driver and the negative terminal driver are separately and independently switchable to provide a current having a magnitude and direction. During a transmission cycle each of the resistance elements has a current of a different magnitude and/or direction than the other resistance elements.

Abstract: A method of combining data from multiple sensors is disclosed. The method includes providing a common control signal to multiple image sensors. Each of the multiple image sensors is responsive to the common control signal to generate image data. The method also includes receiving synchronized data output from each of the multiple image sensors.

Abstract: A termination network for a receiver device is provided to support both D-PHY signaling and N-factorial signaling. The first end of each of a plurality dynamically configurable switches is coupled to a common node. A first end of each of a plurality of resistances is coupled to a second end of a corresponding switch. A plurality of terminals receive differential signals and each terminal is coupled to a corresponding second end of a resistance. Each of a plurality differential receivers is coupled between two terminals of the termination network, wherein a first differential receiver and a second differential receiver are coupled to the same two terminals, the first differential receiver is used when the differential signals use a first type of differential signal encoding, the second differential receiver is used when the differential signals use a second type of differential signal encoding.

Abstract: System, methods and apparatus are described that offer improved performance of a serial bus used for Inter-Integrated Circuit (I2C) and/or camera control interface (CCI) operations. CCI extension (CCIe) devices are described. CCIe devices may be configured as a bus master or as a slave. In one method, a CCIe transmitter may generate a transition number from a set of bits, convert the transition number into a sequence of symbols, and transmit the sequence of symbols in the signaling state of a two-wire serial bus. Timing information may be encoded in the transitions between symbols of consecutive pairs of symbols in the sequence of symbols. For example, each transition may cause a change in the signaling state of at least one wire of the two-wire serial bus. A CCIe receiver may derive a receive clock from the transitions in order to receive and decode the sequence of symbols.

Abstract: System, methods and apparatus are described that include a serial bus, including a serial bus used for Inter-Integrated Circuit (I2C) and/or camera control interface (CCI) operations. The bus has a first line and a second line, a first set of devices coupled to the bus and a second set of devices coupled to the bus. A method of operating the bus includes configuring the first set of devices to use the first line for data transmissions and use the second line for a first clock signal in a first mode of operation, and configuring the second set of devices to use both the first line and the second line for data transmissions while embedding a second clock signal within symbol transitions of the data transmissions in a second mode of operation.

Abstract: System, methods and apparatus are described that offer improved performance of a serial bus used for Inter-Integrated Circuit (I2C) and/or camera control interface (CCI) operations. CCI extension (CCIe) devices are described. CCIe devices may be configured as a bus master or as a slave. In one method, a CCIe transmitter may generate a transition number from a set of bits, convert the transition number into a sequence of symbols, and transmit the sequence of symbols in the signaling state of a two-wire serial bus. Timing information may be encoded in the transitions between symbols of consecutive pairs of symbols in the sequence of symbols. For example, each transition may cause a change in the signaling state of at least one wire of the two-wire serial bus. A CCIe receiver may derive a receive clock from the transitions in order to receive and decode the sequence of symbols.

Abstract: A method of combining data from multiple sensors is disclosed. The method includes receiving lines of image data at an image processor having an input for a single camera. Each line of the image data includes first line data from a first image captured by a first camera and second line data from a second image captured by a second camera. The method also includes generating an output frame having a first section corresponding to line data of the first image and having a second section corresponding to line data of the second image. The first section and the second section are configured to be used to generate a three-dimensional (3D) image format or a 3D video format.

Abstract: A method, an apparatus, and a computer program product are described. The apparatus generates a receive clock signal for receiving data from a multi-wire open-drain link by determining a transition in a signal received from the multi-wire open-drain link, generating a clock pulse responsive to the transition, delaying the clock pulse by a preconfigured first interval if the transition is in a first direction, and delaying the clock by a preconfigured second interval if the transition is in a second direction. The preconfigured first and/or second intervals are configured based on a rise time and/or a fall time associated with the communication interface and may be calibrated by measuring respective delays associated with clock pulses generated for first and second calibration transitions.

Abstract: System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A sequence of data bits is converted into M transition numbers, which are then converted into a sequence of symbols. The sequence of symbols is transmitted received over N wires. A clock signal may be effectively embedded in the transmission of the sequence of symbols. Each of the sequence of symbols may be selected based on a corresponding one of the M transition numbers and a value of a preceding one of the sequence of symbols.

Abstract: A termination network for a receiver device is provided to support both D-PHY signaling and N-factorial signaling. The first end of each of a plurality dynamically configurable switches is coupled to a common node. A first end of each of a plurality of resistances is coupled to a second end of a corresponding switch. A plurality of terminals receive differential signals and each terminal is coupled to a corresponding second end of a resistance. Each of a plurality differential receivers is coupled between two terminals of the termination network, wherein a first differential receiver and a second differential receiver are coupled to the same two terminals, the first differential receiver is used when the differential signals use a first type of differential signal encoding, the second differential receiver is used when the differential signals use a second type of differential signal encoding.

Abstract: A clock recovery circuit is provided comprising a receiver circuit and a clock extraction circuit. The receiver circuit may be adapted to decode a differentially encoded signal on a plurality of data lines, where at least one data symbol is differentially encoded in state transitions of the differentially encoded signal. The clock extraction circuit may be adapted to obtain a clock signal from state transition signals derived from the state transitions while compensating for skew in the different data lines, and masking data state transition glitches.

Abstract: A method for performing multi-wire signaling encoding is provided in which a clock signal is encoded within symbol transitions. A sequence of data bits is converted into a plurality of m transition numbers. Each transition number is converted into a sequential symbol number from a set of sequential symbol numbers. The sequential symbol number is converted into a raw symbol that can be transmitted over a plurality of differential drivers. The raw symbol is transmitted spread over a plurality of n wires, wherein the clock signal is effectively embedded in the transmission of raw symbols since the conversion from transition number into a sequential symbol number guarantees that no two consecutive raw symbols are the same. The raw symbol is guaranteed to have a non-zero differential voltage across all pairs of the plurality of n wires.

Abstract: A termination network circuit for a differential signal transmitter comprises a plurality of n resistance elements and a plurality of differential signal drivers. A first end of each of the resistance elements is coupled at a common node, where n is an integer value and is the number of conductors used to transmit a plurality of differential signals. Each differential signal driver may include a positive terminal driver and a negative terminal driver. The positive terminal driver is coupled to a second end of a first resistance element while the negative terminal driver is coupled to a second end of a second resistance element. The positive terminal driver and the negative terminal driver are separately and independently switchable to provide a current having a magnitude and direction. During a transmission cycle each of the resistance elements has a current of a different magnitude and/or direction than the other resistance elements.

Abstract: An electronic device for parallel image processing using multiple processors is disclosed. The electronic device includes multiple image sensors for providing image data. The electronic device also includes multiple processors for processing segmented image data to produce processed segmented image data. Each processor is dedicated to one of the image sensors. A multiple processor interface is also included. The multiple processor interface maps the image data to the processors, segments the image data to produce the segmented image data and synchronizes the segmented image data to processor clock rates.

Abstract: This disclosure describes barcode scanning techniques for an image capture device. The image capture device may automatically detect a barcode within an image while the image capture device is operating in a non-barcode image capture mode, such a default image capture mode. In one aspect, the detection of the barcode within the image may be based on a combination of identified edges and low intensity regions within the image. The image capture device may configure, based on the detection of the barcode, one or more image capture properties associated with the image capture device to improve a quality at which the images are captured. The image capture device captures the image in accordance with the configured image capture properties. The techniques may effectively provide a universal and integrated front-end for producing improved quality images of barcodes without requiring significant interaction with a user via a complicated user interface.

Abstract: This disclosure describes techniques for detecting a barcode within an image. An image processor may, for example, process an image to detect regions within the image that may be barcodes. The image processor may identify regions of the image that exhibit a high concentration of edges and a high concentration of pixels with low optical intensity co-instantaneously as potential barcodes. The image processor may identify the regions using a number of morphological operations. The image processor may then determine whether the identified regions are actually barcodes by verifying whether the region have unique barcode features. The barcode detection techniques described in this disclosure may be independent of barcode size, location and orientation within the image. Moreover, the use of morphological operations results in faster and more computationally efficient barcode detection, as well as lower computational complexity.

Abstract: Present embodiments contemplate systems, apparatus, and methods to determine a user's preference for depicting a stereoscopic effect. Particularly, certain of the embodiments contemplate receiving user input while displaying a stereoscopic video sequence. The user's preferences may be determined based upon the input. These preferences may then be applied to future stereoscopic depictions.