Patents by Inventor Joseph D. Macri

Joseph D. Macri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230342325
    Abstract: A link controller includes a Peripheral Component Interconnect Express (PCIe) physical layer circuit for coupling to a communication link and providing a data path over the communication link, a first data link layer controller which operates according to a PCIe protocol, and a second data link layer controller which operates according to a non-PCIe protocol. A multiplexer-demultiplexer selectively connects both data link layer controllers to the PCIe physical layer circuit. A protocol translation circuit is coupled between the multiplexer-demultiplexer and the second data link layer controller, the protocol translation circuit receiving traffic data from the second data link layer controller in a non-PCIe format, encapsulating the non-PCIe format in a PCIe format, and passing traffic data to the multiplexer-demultiplexer circuit.
    Type: Application
    Filed: June 30, 2023
    Publication date: October 26, 2023
    Applicants: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Gordon Caruk, Maurice B. Steinman, Gerald R. Talbot, Joseph D. Macri
  • Patent number: 11693813
    Abstract: A link controller includes a Peripheral Component Interconnect Express (PCIe) physical layer circuit for coupling to a communication link and providing a data path over the communication link, a first data link layer controller which operates according to a PCIe protocol, and a second data link layer controller which operates according to a Gen-Z protocol. A multiplexer-demultiplexer selectively connects both data link layer controllers to the PCIe physical layer circuit. A protocol translation circuit is coupled between the multiplexer-demultiplexer and the second data link layer controller, the protocol translation circuit receiving traffic data from the second data link layer controller in a Gen-Z format, encapsulating the Gen-Z format in a PCIe format, and passing traffic data to the multiplexer-demultiplexer circuit.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: July 4, 2023
    Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Gordon Caruk, Maurice B. Steinman, Gerald R. Talbot, Joseph D. Macri
  • Publication number: 20200192853
    Abstract: A link controller includes a Peripheral Component Interconnect Express (PCIe) physical layer circuit for coupling to a communication link and providing a data path over the communication link, a first data link layer controller which operates according to a PCIe protocol, and a second data link layer controller which operates according to a Gen-Z protocol. A multiplexer-demultiplexer selectively connects both data link layer controllers to the PCIe physical layer circuit. A protocol translation circuit is coupled between the multiplexer-demultiplexer and the second data link layer controller, the protocol translation circuit receiving traffic data from the second data link layer controller in a Gen-Z format, encapsulating the Gen-Z format in a PCIe format, and passing traffic data to the multiplexer-demultiplexer circuit.
    Type: Application
    Filed: May 30, 2019
    Publication date: June 18, 2020
    Applicants: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Gordon Caruk, Maurice B. Steinman, Gerald R. Talbot, Joseph D. Macri
  • Patent number: 9342474
    Abstract: A computer system includes a first processor, a second processor, and a common memory connected to the second processor. The computer system is switched from a high performance mode, in which at least a portion of the first processor and at least a portion of components on the second processor are active, to a low power mode, in which at least a portion of the first processor is active and the components on the second processor are inactive. All central processing unit (CPU) cores on the second processor are quiesced. Traffic from the second processor to the common memory is quiesced. Paths used by the first processor to access the common memory are switched from a first path across the second processor to a second path across the second processor.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: May 17, 2016
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Joseph D. Macri, Daniel L. Bouvier
  • Publication number: 20150317269
    Abstract: A computer system includes a first processor, a second processor, and a common memory connected to the second processor. The computer system is switched from a high performance mode, in which at least a portion of the first processor and at least a portion of components on the second processor are active, to a low power mode, in which at least a portion of the first processor is active and the components on the second processor are inactive. All central processing unit (CPU) cores on the second processor are quiesced. Traffic from the second processor to the common memory is quiesced. Paths used by the first processor to access the common memory are switched from a first path across the second processor to a second path across the second processor.
    Type: Application
    Filed: July 13, 2015
    Publication date: November 5, 2015
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Joseph D. Macri, Daniel L. Bouvier
  • Patent number: 9111050
    Abstract: A computer system includes a first processor, a second processor, and a common memory connected to the second processor. The computer system is switched from a high performance mode, in which at least a portion of the first processor and at least a portion of components on the second processor are active, to a low power mode, in which at least a portion of the first processor is active and the components on the second processor are inactive. All central processing unit (CPU) cores on the second processor are quiesced. Traffic from the second processor to the common memory is quiesced. Paths used by the first processor to access the common memory are switched from a first path across the second processor to a second path across the second processor.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: August 18, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Joseph D. Macri, Daniel L. Bouvier
  • Publication number: 20150006782
    Abstract: A computer system includes a first processor, a second processor, and a common memory connected to the second processor. The computer system is switched from a high performance mode, in which at least a portion of the first processor and at least a portion of components on the second processor are active, to a low power mode, in which at least a portion of the first processor is active and the components on the second processor are inactive. All central processing unit (CPU) cores on the second processor are quiesced. Traffic from the second processor to the common memory is quiesced. Paths used by the first processor to access the common memory are switched from a first path across the second processor to a second path across the second processor.
    Type: Application
    Filed: September 16, 2014
    Publication date: January 1, 2015
    Inventors: Joseph D. Macri, Daniel L. Bouvier
  • Patent number: 8856458
    Abstract: A single interconnect is provided between a first processor and a second processor, such that the first processor may access a common memory through the second processor while the second processor can be mostly powered off. The first processor accesses the memory through a memory controller using a standard dynamic random access memory (DRAM) bus protocol. Instead of the memory controller directly connecting to the memory, the access path is through the second processor to the memory. Additionally, a bidirectional communication protocol bus is mapped to the existing DRAM bus signals. When both the first processor and the second processor are active, the bus protocol between the processors switches from the DRAM protocol to the bidirectional communication protocol. This enables the necessary chip-to-chip transaction semantics without requiring the additional cost burden of a dedicated interface for the bidirectional communication protocol.
    Type: Grant
    Filed: December 15, 2009
    Date of Patent: October 7, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Joseph D. Macri, Daniel L. Bouvier
  • Patent number: 8775747
    Abstract: A method and system for performing byte-writes are described, where byte-writes involve writing only particular bytes of a multiple byte write operation. Embodiments include mask data that indicates which bytes are to be written in a byte-write operation. No dedicated mask pin(s) or dedicated mask line(s) are used. In one embodiment, the mask data is transmitted on data lines and store in response to a write_mask command. In one embodiment, the mask data is transmitted as part of the write command.
    Type: Grant
    Filed: March 19, 2013
    Date of Patent: July 8, 2014
    Assignee: ATI Technologies ULC
    Inventors: Joseph D. Macri, Stephen Morein, Ming-Ju E. Lee, Lin Chen
  • Patent number: 8429356
    Abstract: A method and system for performing byte-writes are described, where byte-writes involve writing only particular bytes of a multiple byte write operation. Embodiments include mask data that indicates which bytes are to be written in a byte-write operation. No dedicated mask pin(s) or dedicated mask line(s) are used. In one embodiment, the mask data is transmitted on data lines and store in response to a write_mask command. In one embodiment, the mask data is transmitted as part of the write command.
    Type: Grant
    Filed: February 22, 2006
    Date of Patent: April 23, 2013
    Assignee: ATI Technologies ULC
    Inventors: Joseph D. Macri, Stephen Morein, Ming-Ju E. Lee, Lin Chen
  • Publication number: 20120008671
    Abstract: A system includes a first communication device and a second communication device. The first communication device includes a programmable region. The programmable region of the first communication device is programmed so that an associated signal includes a number of preamble cycles. The second communication device also can include a programmable region. The programmable region of the second communication device can be programmed so that an associated signal includes a number of preamble cycles. The number of preamble cycles can be based on a variety of factors, such as the topology or implementation of the system. In an embodiment, the number of preamble cycles is associated with a data strobe signal, and data is not read or written in response to the data strobe signal until all of the preamble cycles have been transmitted and received.
    Type: Application
    Filed: September 23, 2011
    Publication date: January 12, 2012
    Inventors: Joseph D. Macri, Mark Frankovich
  • Patent number: 8054928
    Abstract: A system includes a first communication device and a second communication device. The first communication device includes a programmable region. The programmable region of the first communication device is programmed so that an associated signal includes a number of preamble cycles. The second communication device also can include a programmable region. The programmable region of the second communication device can be programmed so that an associated signal includes a number of preamble cycles. The number of preamble cycles can be based on a variety of factors, such as the topology or implementation of the system. In an embodiment, the number of preamble cycles is associated with a data strobe signal, and data is not read or written in response to the data strobe signal until all of the preamble cycles have been transmitted and received.
    Type: Grant
    Filed: November 14, 2005
    Date of Patent: November 8, 2011
    Assignee: ATI Technologies, Inc.
    Inventors: Joseph D. Macri, Mark Frankovich
  • Publication number: 20110145492
    Abstract: A single interconnect is provided between a first processor and a second processor, such that the first processor may access a common memory through the second processor while the second processor can be mostly powered off. The first processor accesses the memory through a memory controller using a standard dynamic random access memory (DRAM) bus protocol. Instead of the memory controller directly connecting to the memory, the access path is through the second processor to the memory. Additionally, a bidirectional communication protocol bus is mapped to the existing DRAM bus signals. When both the first processor and the second processor are active, the bus protocol between the processors switches from the DRAM protocol to the bidirectional communication protocol. This enables the necessary chip-to-chip transaction semantics without requiring the additional cost burden of a dedicated interface for the bidirectional communication protocol.
    Type: Application
    Filed: December 15, 2009
    Publication date: June 16, 2011
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Joseph D. Macri, Daniel L. Bouvier
  • Patent number: 7869525
    Abstract: A dynamic bus inversion (DBI) method and system are described. In various embodiments, a transmitter transmits data over a multi-bit high-speed bus to a receiver. In an embodiment, the transmitter determines whether to invert the bus based on the number of data bits that will be transitioning to a new value. If it is determined that the bus is to be inverted, the transmitter encodes a DBI signal on a shared line of the bus. In an embodiment, the shared line is used for different purposes at different times, obviating the need for a dedicated line or pin for the encoded DBI signal. The receiver receives and decodes the DBI signal and, in response, appropriately decodes the received data.
    Type: Grant
    Filed: February 17, 2006
    Date of Patent: January 11, 2011
    Assignee: ATI Technologies, Inc.
    Inventors: Joseph D. Macri, Stephen Morein, Ming-Ju E. Lee, Lin Chen
  • Publication number: 20090251987
    Abstract: In one aspect, there is provided a method for controlling data output by a memory device. The method may include receiving a first clock signal having a first frequency. Moreover, a second and third clock signals may be produced from the first clock signal. The second and third clock signals may have second and third frequencies, respectively, that are about equal to the first frequency. The second and third frequencies may be out of phase relative to each other. A controller may output a first data in response to a rising edge of the second clock signal and output a second data in response to another rising edge of the third clock signal.
    Type: Application
    Filed: June 15, 2009
    Publication date: October 8, 2009
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventor: Joseph D. Macri
  • Patent number: 7564737
    Abstract: In one aspect, there is provided a method for controlling data output by a memory device. The method may include receiving a first clock signal having a first frequency. Moreover, a second and third clock signals may be produced from the first clock signal. The second and third clock signals may have second and third frequencies, respectively, that are about equal to the first frequency. The second and third frequencies may be out of phase relative to each other. A controller may output a first data in response to a rising edge of the second clock signal and output a second data in response to another rising edge of the third clock signal.
    Type: Grant
    Filed: August 30, 2007
    Date of Patent: July 21, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Joseph D. Macri