Patents by Inventor Joseph D. Mendenhall

Joseph D. Mendenhall has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7784002
    Abstract: Systems for using relative positioning of items or components in a structure with dynamic ranges, such as an elastic I/O bus design for an Integrated Circuit (IC), are disclosed. Embodiments may include a user-defined type module having user-defined types representing relative instance positions within a structure. Embodiments may also include a translation helper module to receive information associated with a hierarchy and to return location information associated with the hierarchy and a translation module to translate between a specific location and a relative position of the instance based on one or more user-defined types and location information returned from the translation helper module to generate a list of translated results. Further embodiments of the translation module may include a relative position determiner to translate specific locations to relative positions and may also include a specific location determiner to translate relative positions to specific locations.
    Type: Grant
    Filed: October 17, 2008
    Date of Patent: August 24, 2010
    Assignee: International Business Machines Corporation
    Inventors: Charles L. Alley, Robert B. Likovich, Joseph D. Mendenhall, Chad E. Winemiller
  • Publication number: 20090089728
    Abstract: Systems for using relative positioning of items or components in a structure with dynamic ranges, such as an elastic I/O bus design for an Integrated Circuit (IC), are disclosed. Embodiments may include a user-defined type module having user-defined types representing relative instance positions within a structure. Embodiments may also include a translation helper module to receive information associated with a hierarchy and to return location information associated with the hierarchy and a translation module to translate between a specific location and a relative position of the instance based on one or more user-defined types and location information returned from the translation helper module to generate a list of translated results. Further embodiments of the translation module may include a relative position determiner to translate specific locations to relative positions and may also include a specific location determiner to translate relative positions to specific locations.
    Type: Application
    Filed: October 17, 2008
    Publication date: April 2, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles L. Alley, Robert B. Likovich, JR., Joseph D. Mendenhall, Chad E. Winemiller
  • Patent number: 7461364
    Abstract: Methods and readable media for using relative positioning of items or components in a structure with dynamic ranges, such as an elastic I/O bus design for an Integrated Circuit (IC), are disclosed. Embodiments may include a user-defined type module having user-defined types representing relative instance positions within a structure. Embodiments may also include a translation helper module to receive information associated with a hierarchy and to return location information associated with the hierarchy and a translation module to translate between a specific location and a relative position of the instance based on one or more user-defined types and location information returned from the translation helper module to generate a list of translated results. Further embodiments of the translation module may include a relative position determiner to translate specific locations to relative positions and may also include a specific location determiner to translate relative positions to specific locations.
    Type: Grant
    Filed: April 10, 2006
    Date of Patent: December 2, 2008
    Assignee: International Business Machines Corporation
    Inventors: Charles L. Alley, Robert B. Likovich, Jr., Joseph D. Mendenhall, Chad E. Winemiller
  • Publication number: 20080162998
    Abstract: A test pattern is loaded into a driver data shift register and sent from a driver chip to a receive chip over an M bit bus (0 to M?1). The test pattern is also generated at the receiver chip and used to compare to the actual received data. Failed compares are stored as logic ones in a bit error register (BER). A counter determines the number of failures by counting logic ones from the BER. The contents of a error position counter are latched in a error position latch and used to load a logic one (at the error bit position) into daisy chained self-heal control registers (SCR) in the receiver chip and the driver chip. The SCR sets a logic one into all bit positions after the error bit isolating the failed bit path and adding a spare bit path which is in bit position M.
    Type: Application
    Filed: March 14, 2008
    Publication date: July 3, 2008
    Applicant: International Business Machines Corporation
    Inventors: Robert B. Likovich, Robert J. Reese, Joseph D. Mendenhall, Kenneth J. Barker