Abstract: A CMOS microprocessor chip includes an on-chip single-poly EPROM that is process compatible with the CMOS process used to manufacture the microprocessor. The EPROM is used to store manufacturing and contract related data such as serial number, customer, and process related data such as wafer number test results, binning data, etc. This provides important information for quality and reliability control. The EPROM is also used to control selection of optional microprocessor features such as speed governing, pin-out and I/O bus interface configuration. A third use is for trimming of critical circuit elements and for cache redundancy fault control.

Abstract: A CMOS microprocessor chip includes an on-chip single-poly EPROM that is process-compatible with the CMOS process used to manufacture the microprocessor. The EPROM is used to store manufacturing and contract related data such as serial number, customer, and process related data such as wafer number test results, binning data, etc. This provides important information for quality and reliability control. The EPROM is also used to control selection of optional microprocessor features such as speed governing, pin-out and I/O bus interface configuration. A third use is for trimming of critical circuit elements and for cache redundancy fault control.

Abstract: A voltage converting package for an integrated circuit. The package of the present invention has a voltage converting means for converting a first operating voltage supplied to the package into a second operating voltage which is utilized to power an integrated circuit contained within the package.

Abstract: The specification describes an integrated circuit device that selects its own supply voltage by controlling a programmable power supply. The programmable power supply provides a supply voltage in response to one or more voltage control signals generated by the integrated circuit device. The integrated circuit device includes a voltage control circuit for generating the voltage control signals according to one or more predetermined operational voltages programmed into the integrated circuit device such that the supply voltage is substantially equal to a selected one of the predetermined operational voltages. The integrated circuit device may include a temperature sensor to allow selection of the predetermined operational voltage according to device temperature to avoid speed-limiting voltage and temperature combinations.

Abstract: A global reset circuit especially suitable for integration into a microprocessor and implemented in CMOS technology is disclosed herein. This circuit includes reset circuitry having an input adapted for connection with a direct current power supply voltage which, when activated, rises from its minimum voltage level to its maximum voltage level over a period of time, and an output adapted for connection with at least one circuit component to be reset, for example certain components forming part of a microprocessor. To this end, the circuitry provides a reset signal at its output upon initiation of the power supply voltage and until the power supply voltage reaches a predetermined level, at which time the reset signal is removed. A latching circuit which forms part of the reset circuitry is operated by the power supply voltage in a first state during the presence of the reset signal and in a second, latched state for removing the reset signal.

Abstract: A bootstrapped driver particularly suitable for CMOS integrated circuits. The circuit permits precharging of gates which require bootstrapping in the driver, thus avoiding the time required in prior art circuits to charge relatively large gate capacitance after the input signal is applied to the driver. A circuit is provided to reduce the bootstrapping of the gate after it has begun to reduce possible gate edge aided breakdown. Substantial improvement in rise time or fall time is achieved.

Abstract: A CMOS dynamic RAM is described which uses multiplexing to selectively couple two pairs of bit lines to a single sense amplifier. Both pairs of bit lines are decoupled from the sense amplifier after a word line selects a cell and before sensing occurs in the sense amplifier. Only one pair of bit lines is coupled to the input/output lines of the memory. No dummy cells are employed. The bit lines are charged to one-half the power supply potential. Restoration of potentials on each pair of bit lines occurs at different times, thereby reducing the peak currents to the RAM.