Patents by Inventor Joseph Devore
Joseph Devore has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7554309Abstract: Systems, methods and circuits for regulator minimum load control. In one particular case, a system is provided that includes a load control circuit and a switched load. The load control circuit includes a reference current, and a sense current representative of a load current. In addition, the load control circuit includes a comparator circuit that drives a control signal in response to a comparison between the reference current and the sense current. The switched load is electrically coupled to a load voltage signal to provide loading to the load voltage signal. The switched load is operable to switch between a first loading factor and a second loading factor in response to the control signal.Type: GrantFiled: May 18, 2005Date of Patent: June 30, 2009Assignee: Texas Instruments IncorporatedInventors: John H. Carpenter, Jr., Brett J. Thompsen, Benjamin L. Amey, Zhihong You, Joseph A. Devore
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Patent number: 7516037Abstract: A method evaluating threshold of a data cell in a memory device including a programming locus coupled with the data cell for receiving a programming signal setting a stored signal level in the data cell and responding to a read signal to indicate the stored signal at a read locus; includes the steps of: (a) in no particular order; (1) selecting a test threshold signal; and (2) setting a read signal at a non-read level; (b) applying the test threshold signal to the programming locus; (c) cycling the read signal between a read level and a non-read level while applying the test threshold signal to the programming locus to present at least two test signals at the read locus when the read signal is at the read level; and (d) while cycling, observing whether the at least two test signals manifest a difference greater than a predetermined amount.Type: GrantFiled: May 31, 2007Date of Patent: April 7, 2009Assignee: Texas Instruments IncorporatedInventors: David John Baldwin, Eric Blackall, Joseph Devore, Ross E. Teggatz
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Publication number: 20070240026Abstract: A method evaluating threshold of a data cell in a memory device including a programming locus coupled with the data cell for receiving a programming signal setting a stored signal level in the data cell and responding to a read signal to indicate the stored signal at a read locus; includes the steps of: (a) in no particular order: (1) selecting a test threshold signal; and (2) setting a read signal at a non-read level; (b) applying the test threshold signal to the programming locus; (c) cycling the read signal between a read level and a non-read level while applying the test threshold signal to the programming locus to present at least two test signals at the read locus when the read signal is at the read level; and (d) while cycling, observing whether the at least two test signals manifest a difference greater than a predetermined amount.Type: ApplicationFiled: May 31, 2007Publication date: October 11, 2007Applicant: Texas Instruments IncorporatedInventors: David Baldwin, Eric Blackall, Joseph Devore, Ross Teggatz
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Patent number: 7269528Abstract: A method evaluating threshold of a data cell in a memory device including a programming locus coupled with the data cell for receiving a programming signal setting a stored signal level in the data cell and responding to a read signal to indicate the stored signal at a read locus; includes the steps of: (a) in no particular order: (1) selecting a test threshold signal; and (2) setting a read signal at a non-read level; (b) applying the test threshold signal to the programming locus; (c) cycling the read signal between a read level and a non-read level while applying the test threshold signal to the programming locus to present at least two test signals at the read locus when the read signal is at the read level; and (d) while cycling, observing whether the at least two test signals manifest a difference greater than a predetermined amount.Type: GrantFiled: May 28, 2005Date of Patent: September 11, 2007Assignee: Texas Instruments IncorporatedInventors: David John Baldwin, Eric Blackall, Joseph Devore, Ross E. Teggatz
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Publication number: 20060271323Abstract: A method evaluating threshold of a data cell in a memory device including a programming locus coupled with the data cell for receiving a programming signal setting a stored signal level in the data cell and responding to a read signal to indicate the stored signal at a read locus; includes the steps of: (a) in no particular order: (1) selecting a test threshold signal; and (2) setting a read signal at a non-read level; (b) applying the test threshold signal to the programming locus; (c) cycling the read signal between a read level and a non-read level while applying the test threshold signal to the programming locus to present at least two test signals at the read locus when the read signal is at the read level; and (d) while cycling, observing whether the at least two test signals manifest a difference greater than a predetermined amount.Type: ApplicationFiled: May 28, 2005Publication date: November 30, 2006Inventors: David Baldwin, Eric Blackall, Joseph Devore, Ross Teggatz
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Publication number: 20060261793Abstract: Systems, methods and circuits for regulator minimum load control. In one particular case, a system is provided that includes a load control circuit and a switched load. The load control circuit includes a reference current, and a sense current representative of a load current. In addition, the load control circuit includes a comparator circuit that drives a control signal in response to a comparison between the reference current and the sense current. The switched load is electrically coupled to a load voltage signal to provide loading to the load voltage signal. The switched load is operable to switch between a first loading factor and a second loading factor in response to the control signal.Type: ApplicationFiled: May 18, 2005Publication date: November 23, 2006Applicant: Texas Instruments IncorporatedInventors: John Carpenter, Brett Thompsen, Benjamin Amey, Zhihong You, Joseph Devore
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Patent number: 7133268Abstract: System and method for controlling current across a load. A preferred embodiment comprises a current varying circuit (such as current varying circuit 525) that can create a sequence of voltage drops in a driver circuit (such as the driver circuit 505) coupled to an inductive load (such as the inductive load 535). By initially producing a large voltage drop and then stepping the voltage drop down gradually, the current in the inductive load can be rapidly removed without producing a current undershoot, which, in certain applications, can result in unwanted noise and vibration.Type: GrantFiled: December 1, 2003Date of Patent: November 7, 2006Assignee: Texas Instruments IncorporatedInventors: Rex M. Teggatz, Wayne Tien-Feng Chen, Joseph Devore
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Patent number: 6940131Abstract: The present invention includes a MOS device (100) that has a P-type substrate (102) and an N-type drain region (104) formed within the substrate (102). An annular N-type source region (106) generally surrounds the drain region (104). The source region (106) serves as both the source for the MOS device (100) and a sacrificial collector guard ring for an electrostatic discharge protection circuit. An annular gate region (110) generally surrounds the drain region (104) and is electrically insulated from the drain region (104) and electrically connected to the source region (106). An annular P-type bulk region (108) generally surrounds the source region (106) and is electrically connected to the source region (106).Type: GrantFiled: June 30, 2003Date of Patent: September 6, 2005Assignee: Texas Instruments IncorporatedInventors: David John Baldwin, Joseph A. Devore, Robert Steinhoff, Jonathan Brodsky
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Publication number: 20050117265Abstract: System and method for controlling current across a load. A preferred embodiment comprises a current varying circuit (such as current varying circuit 525) that can create a sequence of voltage drops in a driver circuit (such as the driver circuit 505) coupled to an inductive load (such as the inductive load 535). By initially producing a large voltage drop and then stepping the voltage drop down gradually, the current in the inductive load can be rapidly removed without producing a current undershoot, which, in certain applications, can result in unwanted noise and vibration.Type: ApplicationFiled: December 1, 2003Publication date: June 2, 2005Inventors: Rex Teggatz, Wayne Tien-Feng Chen, Joseph Devore
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Publication number: 20050007216Abstract: The present invention includes a MOS device (100) that has a P-type substrate (102) and an N-type drain region (104) formed within the substrate (102). An annular N-type source region (106) generally surrounds the drain region (104). The source region (106) serves as both the source for the MOS device (100) and a sacrificial collector guard ring for an electrostatic discharge protection circuit. An annular gate region (110) generally surrounds the drain region (104) and is electrically insulated from the drain region (104) and electrically connected to the source region (106). An annular P-type bulk region (108) generally surrounds the source region (106) and is electrically connected to the source region (106).Type: ApplicationFiled: June 30, 2003Publication date: January 13, 2005Inventors: David Baldwin, Joseph Devore, Robert Steinhoff, Jonathan Brodsky
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Publication number: 20040150034Abstract: An EEPROM cell (10) formed on a substrate (18) using conventional process steps is provided. The cell (10) includes first (12) and second (14) conductive regions in the substrate (18) below the substrate's outer surface (28), and the first (12) and second (14) conductive regions are laterally displaced from one another by a predetermined distance (32). The cell (10) also includes an insulating layer (20) outwardly from the outer surface (28) of the substrate (18) positioned so that its edges are substantially in alignment between the first (12) and second (14) conductive regions. The cell (10) further includes a floating gate layer (22) outwardly from the insulating layer (20) and in substantially the same shape as the insulating layer (20). The cell (10) also includes a diffusion region (24 or 26) that extends laterally from at least one of the first (12) and second (14) conductive regions so as to overlap with the insulating layer (20).Type: ApplicationFiled: January 7, 2004Publication date: August 5, 2004Inventors: Andrew Marshall, Joseph A. Devore, Ross E. Teggatz, Wayne T. Chen, Ricky D. Jordanger
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Patent number: 6600205Abstract: A high-breakdown voltage transistor (30; 30′) is disclosed. The transistor (30; 30′) is formed into a well arrangement in which a shallow, heavily doped, well (44) is disposed at least partially within a deeper, more lightly-doped well (50), both formed into an epitaxial layer (43) of the substrate (42). The deep well (50) is also used, by itself, for the formation of high-voltage transistors, while the shallower well (44) is used by itself in low-voltage, high-performance transistors. This construction permits the use of high-performance, and precisely matching, transistors in high bias voltage applications, without fear of body-to-substrate (or “back-gate-to-substrate”) junction breakdown.Type: GrantFiled: February 1, 2002Date of Patent: July 29, 2003Inventors: John H. Carpenter, Jr., Joseph A. Devore, Toru Tanaka
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Patent number: 6486740Abstract: One aspect of the invention is an integrated circuit (10 or 110) comprising an amplifier (11 or 111) having at least two poles in its frequency response and an output impedance compensation circuit (M1A, M2, M3, AC1 or M1A, M2, M3, M4, AC1) coupled to an output node (30) of the amplifier (11 or 111). The output impedance compensation circuit (M1A, M2, M3, AC1 or M1A, M2, M3, M4, AC1) is operable to create a feedback signal proportional to the impedance of an output load (50) coupled to the output node (30), and create a zero in the frequency response of the amplifier (11 or 111) in response to the feedback signal between the at least two poles.Type: GrantFiled: August 28, 2000Date of Patent: November 26, 2002Assignee: Texas Instruments IncorporatedInventors: David J. Baldwin, Ross E. Teggatz, Joseph A. Devore
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Patent number: 6469884Abstract: An integrated circuit (10) having at least one programmable fuse (F1) and ESD circuitry (MN3, MN1) preventing the fuse (F1) from being unintentionally blown when a voltage transient exists on a main voltage potential (Vmain). The ESD circuitry preferably comprises of MOSFET switches which are coupled to turn on quicker than a main fuse programming switch (MNmain) due to the voltage transient, thereby insuring that the main switch remains off during the voltage transient to prevent the unintentional blowing of the fuse F1. The circuit is well suited for programmable logic device (PLDs), allowing for read voltages as low as 6 volts, and allowing for programming voltages as high as 40 volts.Type: GrantFiled: December 24, 1999Date of Patent: October 22, 2002Assignee: Texas Instruments IncorporatedInventors: John H. Carpenter, Jr., Joseph A. Devore, Reed Adams, Ross Teggatz
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Publication number: 20020145173Abstract: A high-breakdown voltage transistor (30; 30′) is disclosed. The transistor (30; 30′) is formed into a well arrangement in which a shallow, heavily doped, well (44) is disposed at least partially within a deeper, more lightly-doped well (50), both formed into an epitaxial layer (43) of the substrate (42). The deep well (50) is also used, by itself, for the formation of high-voltage transistors, while the shallower well (44) is used by itself in low-voltage, high-performance transistors. This construction permits the use of high-performance, and precisely matching, transistors in high bias voltage applications, without fear of body-to-substrate (or “back-gate-to-substrate”) junction breakdown.Type: ApplicationFiled: February 1, 2002Publication date: October 10, 2002Inventors: John H. Carpenter, Joseph A. Devore, Toru Tanaka, Ross E. Teggatz
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Patent number: 6407626Abstract: Provided is a symmetrical filter that uses a single comparator. In addition to a voltage divider, a current regulator, and a comparator, the filter of the invention provides control logic that turns on or off a pull up switch and/or pull down switch in order to fully charge or fully discharge a capacitor. Accordingly, in one aspect, the invention is a control logic for a symmetrical filter. Furthermore, timing logic is provided to provide for a more rigorous symmetrical filter performance.Type: GrantFiled: November 17, 2000Date of Patent: June 18, 2002Assignee: Texas Instruments IncorporatedInventors: John H. Carpenter, Jr., Joseph A. Devore, Tohru Tanaka, Ross E. Teggatz
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Patent number: 6376870Abstract: A high-breakdown voltage transistor (30; 30′) is disclosed. The transistor (30; 30′) is formed into a well arrangement in which a shallow, heavily doped, well (44) is disposed at least partially within a deeper, more lightly-doped well (50), both formed into an epitaxial layer (43) of the substrate (42). The deep well (50) is also used, by itself, for the formation of high-voltage transistors, while the shallower well (44) is used by itself in low-voltage, high-performance transistors. This construction permits the use of high-performance, and precisely matching, transistors in high bias voltage applications, without fear of body-to-substrate (or “back-gate-to-substrate”) junction breakdown.Type: GrantFiled: September 8, 2000Date of Patent: April 23, 2002Assignee: Texas Instruments IncorporatedInventors: John H. Carpenter, Jr., Joseph A. Devore, Toru Tanaka, Ross E. Teggatz
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Patent number: 6373343Abstract: An integrated circuit (10) is disclosed comprising a fundamental frequency oscillator comprising a reference node (32) whose voltage varies between a high threshold and a low threshold. The fundamental frequency oscillator is operable to generate a first output at the fundamental frequency on a first output node (36). The integrated circuit (10) also comprises a circuit (C2) coupled to the reference node. The circuit (C2) is operable to sense the voltage at the reference node (32), to determine when the voltage exceeds an intermediate threshold between the high threshold and the low threshold, and to generate a second output in response to the determination. The integrated circuit (10) also comprises logic (40) coupled to the circuit (C2) and load circuitry (50) coupled to the logic (40). The logic (40) is operable to generate an output signal at an output frequency greater than the fundamental frequency in response to the second output and the first output.Type: GrantFiled: August 28, 2000Date of Patent: April 16, 2002Assignee: Texas Instruments IncorporatedInventors: David J. Baldwin, Christopher M. Cooper, Joseph A. Devore, Ross E. Teggatz
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Patent number: 6373094Abstract: An EEPROM cell (10) formed on a substrate (18) using conventional process steps is provided. The cell (10) includes first (12) and second (14) conductive regions in the substrate (18) below the substrate's outer surface (28), and the first (12) and second (14) conductive regions are laterally displaced from one another by a predetermined distance (32). The cell (10) also includes an insulating layer (20) outwardly from the outer surface (28) of the substrate (18) positioned so that its edges are substantially in alignment between the first (12) and second (14) conductive regions. The cell (10) further includes a floating gate layer (22) outwardly from the insulating layer (20) and in substantially the same shape as the insulating layer (20). The cell (10) also includes a diffusion region (24 or 26) that extends laterally from at least one of the first (12) and second (14) conductive regions so as to overlap with the insulating layer (20).Type: GrantFiled: July 18, 2001Date of Patent: April 16, 2002Assignee: Texas Instruments IncorporatedInventors: Andrew Marshall, Joseph A. Devore, Ross E. Teggatz, Wayne T. Chen, Ricky D. Jordanger
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Patent number: 6324044Abstract: A controlled area network (CAN) driver provides improved symmetry between its differential output signals CAN-H and CAN-L, and provides protection for its low voltage devices from voltage transients occurring on its output lines. A plurality of CAN drivers 80 are serially interconnected to form a driver system, wherein each downstream driver stage receives a time-delayed form of the digital input signal TxD, each stage providing a time-delayed contribution to the differential output signals of the overall driver system.Type: GrantFiled: May 5, 1999Date of Patent: November 27, 2001Assignee: Texas Instruments IncorporatedInventors: Ross E. Teggatz, Joseph A. Devore, Timothy J. Legat, Timothy P. Pauletti, David J. Baldwin