Patents by Inventor Joseph Doller

Joseph Doller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SSD WITH REDUCED SECURE ERASE TIME AND ENDURANCE STRESS
    Publication number: 20230099202
    Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to set an erase voltage for a first block of a persistent storage media to a default erase voltage, determine if the first block of the persistent storage media is identified for a secure erase operation, and set the erase voltage for the first block of the persistent storage media to a shallow erase voltage if the first block of the persistent storage media is identified for the secure erase operation, where the shallow erase voltage corresponds to a weaker erase operation relative to the default erase voltage. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: October 3, 2022
    Publication date: March 30, 2023
    Inventors: Joseph Doller, Kristopher Gaewsky, Byeongkyu Cho
  • SSD with reduced secure erase time and endurance stress
    Patent number: 11462273
    Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to set an erase voltage for a first block of a persistent storage media to a default erase voltage, determine if the first block of the persistent storage media is identified for a secure erase operation, and set the erase voltage for the first block of the persistent storage media to a shallow erase voltage if the first block of the persistent storage media is identified for the secure erase operation, where the shallow erase voltage corresponds to a weaker erase operation relative to the default erase voltage. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: October 4, 2022
    Assignee: Intel Corporation
    Inventors: Joseph Doller, Kristopher Gaewsky, Byeongkyu Cho
  • SSD WITH REDUCED SECURE ERASE TIME AND ENDURANCE STRESS
    Publication number: 20200273525
    Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to set an erase voltage for a first block of a persistent storage media to a default erase voltage, determine if the first block of the persistent storage media is identified for a secure erase operation, and set the erase voltage for the first block of the persistent storage media to a shallow erase voltage if the first block of the persistent storage media is identified for the secure erase operation, where the shallow erase voltage corresponds to a weaker erase operation relative to the default erase voltage. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: May 14, 2020
    Publication date: August 27, 2020
    Applicant: Intel Corporation
    Inventors: Joseph Doller, Kristopher Gaewsky, Byeongkyu Cho