Abstract: A switched frequency divider is disclosed comprising an array of bistable devices which are linked together so as to propagate through the array a low or high signal applied to an input to the array, first gating means for inserting at least one more bistable device into the array, and second gating means for making such an insertion only when the output of the array completes a cycle. To provide for an output wave form that has approximately a 50 percent duty cycle, the bistable devices are coupled togther in the form of a Johnson counter. To permit a change in the divisor only upon the completion of an output cycle, the second gating means is a bistable device which reads an incoming control signal only when the output of the Johnson counter makes a specified change in state. Advantageously, the switched frequency divider may be used as an FSK modulator to generate different AC frequencies from a single AC input signal in response to a digital data signal applied to the divider as said control signal.