Abstract: A floating CMOS input circuit is disclosed that does not draw direct current. The floating CMOS input circuit comprises a first inverter circuit that is capable of being coupled to an input voltage (Vin) and an n-channel pull-down transistor (N1) that is coupled to the first inverter circuit. The n-channel pull-down transistor (N1) pulls the input voltage (Vin) on the first inverter circuit to a hard ground when the input voltage (Vin) is not driven high. This eliminates the leakage of direct current in the first inverter circuit. The floating CMOS input circuit also powers up in a known state.

Abstract: A variable drive strength hysteresis input circuit is disclosed that comprises pull-up circuitry and pull-down circuitry. A variable drive strength circuit changes the pull-up drive strength and the pull-down drive strength in response to receiving an input voltage signal that transitions either from a low level to a high level or from a high level to a low level. In one advantageous embodiment the variable drive strength hysteresis input circuit comprises four p-channel MOSFET transistors and four n-channel MOSFET transistors. The invention efficiently reduces transition noise in the inputs to an integrated circuit chip.

Abstract: For use in an integrated circuit interface to a memory device, there is disclosed an input circuit having an input interface that is capable of receiving one of a high speed, high power signal and a low speed, low power signal. The input circuit of the present invention is capable of preventing direct current leakage within the input circuit when the input circuit is operating in a low speed, low power mode. The input circuit of the present invention comprises a multiplexer that is capable of receiving both high speed, high power signals and low speed, low power signals. The input circuit of the present invention also comprises a switch that is capable of preventing a high speed, high power signal from causing direct current leakage within the input circuit when the input circuit is operating in a low speed, low power mode.

Abstract: For use in an integrated circuit interface to a memory device, there is disclosed an input circuit having an input interface that is capable of receiving one of a high speed, high power signal and a low speed, low power signal. The input circuit of the present invention is capable of preventing direct current leakage within the input circuit when the input circuit is operating in a low speed, low power mode. The input circuit of the present invention comprises a multiplexer that is capable of receiving both high speed, high power signals and low speed, low power signals. The input circuit of the present invention also comprises a switch that is capable of preventing a high speed, high power signal from causing direct current leakage within the input circuit when the input circuit is operating in a low speed, low power mode.

Abstract: An apparatus including an overvoltage protection circuit is provided that comprises an input terminal configured to convey an input voltage, an output terminal configured to convey an output voltage, a buffer circuit, coupled between the input terminal and the output terminal, configured to receive and buffer the input voltage and in accordance therewith provide the output voltage, and a voltage sensing circuit, coupled to the input terminal and the buffer circuit, configured to sense the input voltage and in accordance therewith maintain the buffer circuit in a predetermined voltage range.

Abstract: An input structure protects an Integrated Circuit (IC) against increases in the IC pad voltage when the supply voltage to the IC is tuned off. The input structure includes circuitry for transferring either a divided-down pad voltage or the positive supply voltage to a buffer circuitry. The buffer circuitry receives the voltage transferred thereto and lowers the pad voltage. The lowered pad voltage generated by the buffer circuitry is subsequently applied to the IC.