Patents by Inventor Joseph E. Ervin

Joseph E. Ervin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8441048
    Abstract: The present invention provides a horizontally depleted Metal Semiconductor Field Effect Transistor (MESFET). A drain region, a source region, and a channel region are formed in the device layer such that the drain region and the source region are spaced apart from one another and the channel region extends between the drain region and the source region. First and second gate contacts are formed in the device layer on either side of the channel region, and as such, the first and second gate contacts will also reside between opposing portions of the source and drain regions. With this configuration, voltages applied to the first and second gate contacts effectively control vertical depletion regions, which form on either side of the channel region.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: May 14, 2013
    Assignee: Arizona Board of Regents for and on behalf of Arizona State University
    Inventors: Joseph E. Ervin, Trevor John Thornton
  • Patent number: 8299515
    Abstract: Aspects of the invention provide for methods of forming a deep trench capacitor structure. In one embodiment, aspects of the invention include a method of forming a deep trench capacitor structure, including: forming a deep trench within a semiconductor substrate; depositing a first liner within the deep trench; filling a lower portion of the deep trench with a filler material; depositing a second liner within an upper portion of the deep trench; removing the filler material, such that the lower portion of the deep trench includes only the first liner and the upper portion of the deep trench includes the first liner and the second liner; forming a high doped region around the lower portion of the deep trench; and removing the first liner within the lower portion of the deep trench and the second liner within the upper portion of the deep trench.
    Type: Grant
    Filed: February 8, 2011
    Date of Patent: October 30, 2012
    Assignee: International Business Machines Corporation
    Inventors: Joseph E. Ervin, Yanli Zhang
  • Publication number: 20120199945
    Abstract: Aspects of the invention provide for methods of forming a deep trench capacitor structure. In one embodiment, aspects of the invention include a method of forming a deep trench capacitor structure, including: forming a deep trench within a semiconductor substrate; depositing a first liner within the deep trench; filling a lower portion of the deep trench with a filler material; depositing a second liner within an upper portion of the deep trench; removing the filler material, such that the lower portion of the deep trench includes only the first liner and the upper portion of the deep trench includes the first liner and the second liner; forming a high doped region around the lower portion of the deep trench; and removing the first liner within the lower portion of the deep trench and the second liner within the upper portion of the deep trench.
    Type: Application
    Filed: February 8, 2011
    Publication date: August 9, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Joseph E. Ervin, Yanli Zhang
  • Publication number: 20100320508
    Abstract: The present invention provides a horizontally depleted Metal Semiconductor Field Effect Transistor (MESPET). A drain region, a source region, and a channel region are formed in the device layer such that the drain region and the source region are spaced apart from one another and the channel region extends between the drain region and the source region. First and second gate contacts are formed in the device layer on either side of the channel region, and as such, the first and second gate contacts will also reside between opposing portions of the source and drain regions. With this configuration, voltages applied to the first and second gate contacts effectively control vertical depletion regions, which form on either side of the channel region.
    Type: Application
    Filed: September 12, 2008
    Publication date: December 23, 2010
    Applicant: Arizona Board of Regents for and on behalf of Arizona State University
    Inventors: Joseph E. Ervin, Trevor John Thornton