Abstract: An apparatus that moves stimulus data and response data between a memory and a device under test (DUT) over a plurality of data transfer banks. In a first mode the data transfer banks output the stimulus data to the DUT as respective independent banks of serial stimulus data channels, and write the response data into the memory responsive to data provided as respective independent banks of channels of serial data from the DUT. In a second mode the data transfer banks output the stimulus data to the DUT as a single bank of combined serial stimulus data channels, and write the response data into the memory responsive to the data provided as a combined single bank of channels of serial data from the DUT.

Abstract: An apparatus that moves stimulus data and response data between a memory and a device under test (DUT) over a plurality of data transfer banks. In a first mode the data transfer banks output the stimulus data to the DUT as respective independent banks of serial stimulus data channels, and write the response data into the memory responsive to data provided as respective independent banks of channels of serial data from the DUT. In a second mode the data transfer banks output the stimulus data to the DUT as a single bank of combined serial stimulus data channels, and write the response data into the memory responsive to the data provided as a combined single bank of channels of serial data from the DUT.

Abstract: An embedded control system executed by a microprocessor prevents, the performance of a critical operation unless selected control conditions are properly satisfied. A polite request to perform the critical operation may require the setting of various multi-bit flags indicative of a normal polite entry and does require the issuance of a uniquely identifiable action. A protection circuit distinguishes the uniquely identifiable action and initiates checks of the control conditions. These control conditions may include not only the values of the various multi-bit flags, but other checks indicative of normal operation. If the controlling conditions are met a confirmation stimulus, precisely timed relative to the uniquely identifiable action, satisfies the protection circuit, which then enables the appropriate hardware to perform the critical operation.