Patents by Inventor Joseph Ellis

Joseph Ellis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8138531
    Abstract: Pixel sensor cells, method of fabricating pixel sensor cells and design structure for pixel sensor cells. The pixel sensor cells including: a photodiode body in a first region of a semiconductor layer; a floating diffusion node in a second region of the semiconductor layer, a third region of the semiconductor layer between and abutting the first and second regions; and dielectric isolation in the semiconductor layer, the dielectric isolation surrounding the first, second and third regions, the dielectric isolation abutting the first, second and third regions and the photodiode body, the dielectric isolation not abutting the floating diffusion node, portions of the second region intervening between the dielectric isolation and the floating diffusion node.
    Type: Grant
    Filed: September 17, 2009
    Date of Patent: March 20, 2012
    Assignee: International Business Machines Corporation
    Inventors: James William Adkisson, John Joseph Ellis-Monaghan, Mark David Jaffe, Richard John Rassel
  • Patent number: 8110875
    Abstract: A structure for dissipating charge during fabrication of an integrated circuit. The structure includes: a substrate contact in a semiconductor substrate; one or more wiring levels over the substrate; one or more electrically conductive charge dissipation structures extending from a top surface of an uppermost wiring level of the one or more wiring levels through each lower wiring level of the one or more wiring levels to and in electrical contact with the substrate contact; and circuit structures in the substrate and in the one or more wiring layers, the charge dissipation structures not electrically contacting any the circuit structures in any of the one or more wiring levels, the one or more charge dissipation structures dispersed between the circuit structures.
    Type: Grant
    Filed: July 2, 2008
    Date of Patent: February 7, 2012
    Assignee: International Business Machines Corporation
    Inventors: John Joseph Ellis-Monaghan, Jeffrey Peter Gambino, Timothy Dooling Sullivan, Steven Howard Voldman
  • Patent number: 7923750
    Abstract: A pixel sensor cell, a method for fabricating or operating the pixel sensor cell and a design structure for fabricating the pixel sensor cell each include a semiconductor substrate that includes a photoactive region separated from a floating diffusion region by a channel region. At least one gate dielectric is located upon the semiconductor substrate at least in-part interposed between the photoactive region and the floating diffusion region, and at least one optically transparent gate is located upon the gate dielectric and at least in-part over the channel region. Preferably, the at least one gate dielectric is also located over the photoactive region and the at least one optically transparent gate is also located at least in-part over the photoactive region, to provide enhanced charge transfer capabilities within the pixel sensor cell, which is typically a CMOS pixel sensor cell.
    Type: Grant
    Filed: June 16, 2008
    Date of Patent: April 12, 2011
    Assignee: International Business Machines Corporation
    Inventors: James William Adkisson, Rajendran Krishnasamy, John Joseph Ellis-Monaghan, Solomon Mulugeta, Charles Francis Musante, Richard J. Rassel
  • Publication number: 20110062542
    Abstract: Pixel sensor cells, method of fabricating pixel sensor cells and design structure for pixel sensor cells. The pixel sensor cells including: a photodiode body in a first region of a semiconductor layer; a floating diffusion node in a second region of the semiconductor layer, a third region of the semiconductor layer between and abutting the first and second regions; and dielectric isolation in the semiconductor layer, the dielectric isolation surrounding the first, second and third regions, the dielectric isolation abutting the first, second and third regions and the photodiode body, the dielectric isolation not abutting the floating diffusion node, portions of the second region intervening between the dielectric isolation and the floating diffusion node.
    Type: Application
    Filed: September 17, 2009
    Publication date: March 17, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James William Adkisson, John Joseph Ellis-Monaghan, Mark David Jaffe, Richard John Rassel
  • Publication number: 20110007371
    Abstract: Disclosed are methods (900) and apparatuses (600) for determining a location of a graphical object (2220) printed onto a print medium (230), said graphical object comprising a plurality of object marks, the method comprising the steps of superposing a two-dimensional reference pattern (710) having a pre-defined degree of accuracy over the printed graphical object, the two-dimensional reference pattern comprising a plurality of pattern marks (770); scanning the superposed printed graphical object and reference pattern to produce a scanned image (2400); determining a location coordinate (2923) of the graphical object in the scanned image (2400); and refining the location coordinate dependent upon the scanned reference pattern to determine a reference pattern coordinate (2904?) associated with the location coordinate (2923). Also disclosed are methods (1800), apparatuses, and computer program products for determining a head size (420) of a print head (3110) of a printer (3100) using the aforementioned method.
    Type: Application
    Filed: December 9, 2009
    Publication date: January 13, 2011
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Ben Yip, Paul Joseph Ellis, Son Thai
  • Publication number: 20100244132
    Abstract: A method of normalizing strain in semiconductor devices and normalized strain semiconductor devices. The method includes: forming first and second field effect transistors of an integrated circuit; forming a stress layer over the first and second field effect transistors, the stress layer inducing strain in channel regions of the first and second field effect transistors; and selectively thinning the stress layer over at least a portion of the second field effect transistor.
    Type: Application
    Filed: November 20, 2009
    Publication date: September 30, 2010
    Applicant: International Business Machines Corporation
    Inventors: Bruce Balch, Kerry Bernstein, John Joseph Ellis-Monaghan, Nazmul Habib
  • Publication number: 20090309143
    Abstract: A pixel sensor cell, a method for fabricating or operating the pixel sensor cell and a design structure for fabricating the pixel sensor cell each include a semiconductor substrate that includes a photoactive region separated from a floating diffusion region by a channel region. At least one gate dielectric is located upon the semiconductor substrate at least in-part interposed between the photoactive region and the floating diffusion region, and at least one optically transparent gate is located upon the gate dielectric and at least in-part over the channel region. Preferably, the at least one gate dielectric is also located over the photoactive region and the at least one optically transparent gate is also located at least in-part over the photoactive region, to provide enhanced charge transfer capabilities within the pixel sensor cell, which is typically a CMOS pixel sensor cell.
    Type: Application
    Filed: June 16, 2008
    Publication date: December 17, 2009
    Applicant: International Business Machines Corporation
    Inventors: James William Adkisson, Rajendran Krishnasamy, John Joseph Ellis-Monaghan, Solomon Mulugeta, Charles Francis Musante, Richard J. Rassel
  • Publication number: 20090311822
    Abstract: A pixel sensor cell, a method for fabricating or operating the pixel sensor cell and a design structure for fabricating the pixel sensor cell each include a semiconductor substrate that includes a photoactive region separated from a floating diffusion region by a channel region. At least one gate dielectric is located upon the semiconductor substrate at least in-part interposed between the photoactive region and the floating diffusion region, and at least one optically transparent gate is located upon the gate dielectric and at least in-part over the channel region. Preferably, the at least one gate dielectric is also located over the photoactive region and the at least one optically transparent gate is also located at least in-part over the photoactive region, to provide enhanced charge transfer capabilities within the pixel sensor cell, which is typically a CMOS pixel sensor cell.
    Type: Application
    Filed: June 16, 2008
    Publication date: December 17, 2009
    Applicant: International Business Machines Corporation
    Inventors: James William Adkisson, Rajendran Krishnasamy, John Joseph Ellis-Monaghan, Solomon Mulugeta, Charles Francis Musante, Richard J. Rassel
  • Patent number: 7521280
    Abstract: A method according to one embodiment includes forming a photosensitive region on an substrate; forming at least one dielectric layer upon the photosensitive region; simultaneously forming and patterning a metal layer upon the photosensitive region; wherein a first portion of the metal layer is formed upon the photosensitive region and serves as an optical reflector; wherein a second portion of the metal layer is formed in a transfer gate region and serves as a metal gate electrode for a transfer gate transistor.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: April 21, 2009
    Assignee: International Business Machines Corporation
    Inventors: Brent Alan Anderson, John Joseph Ellis-Monaghan, Edward J. Nowak
  • Publication number: 20080265422
    Abstract: A structure for dissipating charge during fabrication of an integrated circuit. The structure includes: a substrate contact in a semiconductor substrate; one or more wiring levels over the substrate; one or more electrically conductive charge dissipation structures extending from a top surface of an uppermost wiring level of the one or more wiring levels through each lower wiring level of the one or more wiring levels to and in electrical contact with the substrate contact; and circuit structures in the substrate and in the one or more wiring layers, the charge dissipation structures not electrically contacting any the circuit structures in any of the one or more wiring levels, the one or more charge dissipation structures dispersed between the circuit structures.
    Type: Application
    Filed: July 2, 2008
    Publication date: October 30, 2008
    Inventors: John Joseph Ellis-Monaghan, Jeffrey Peter Gambino, Timothy Dooling Sullivan, Steven Howard Voldman
  • Publication number: 20070123396
    Abstract: An exercise treadmill of the type having an endless moveable surface looped around rollers or pulleys to form an upper run and a lower run, the movable surface being rotated when one of the rollers or pulleys is rotated, an exercise surface on for walking or running while exercising, and a weight resistance means for simulating the dragging or pulling of a load, wherein the endless movable surface moves in a direction simulating walking or running backwards.
    Type: Application
    Filed: March 20, 2006
    Publication date: May 31, 2007
    Inventor: Joseph Ellis
  • Publication number: 20070123395
    Abstract: An exercise treadmill of the type having an endless moveable surface looped around rollers or pulleys to form an upper run and a lower run, the movable surface being rotated when one of the rollers or pulleys is rotated, an exercise surface on for walking or running while exercising, and a weight resistance means for simulating the dragging or pulling of a load, wherein the endless movable surface moves in a direction simulating walking or running backwards.
    Type: Application
    Filed: November 30, 2005
    Publication date: May 31, 2007
    Inventor: Joseph Ellis
  • Patent number: 6936910
    Abstract: A method and a BICMOS structure are provided. The BiCMOS structure includes an SOI substrate having a bottom Si-containing layer, a buried insulating layer located atop the bottom Si-containing layer, a top Si-containing layer atop the buried insulating layer and a sub-collector which is located in an upper surface of the bottom Si-containing layer. The sub-collector is in contact with a bottom surface of the buried insulating layer.
    Type: Grant
    Filed: March 23, 2004
    Date of Patent: August 30, 2005
    Assignee: International Business Machines Corporation
    Inventors: John Joseph Ellis-Monaghan, Alvin Jose Joseph, Qizhi Liu, Kirk David Peterson
  • Publication number: 20040222486
    Abstract: A method and a BICMOS structure are provided. The BiCMOS structure includes an SOI substrate having a bottom Si-containing layer, a buried insulating layer located atop the bottom Si-containing layer, a top Si-containing layer atop the buried insulating layer and a sub-collector which is located in an upper surface of the bottom Si-containing layer. The sub-collector is in contact with a bottom surface of the buried insulating layer.
    Type: Application
    Filed: March 23, 2004
    Publication date: November 11, 2004
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John Joseph Ellis-Monaghan, Alvin Jose Joseph, Qizhi Liu, Kirk David Peterson
  • Patent number: 6705017
    Abstract: An apparatus having a foot, a reciprocating saw and a housing. Between the foot and the housing there are means for releasable mounting the foot on the housing, characterized in that the releasable mounting means have a first coupling member connected to the foot and, co-acting therewith, a second coupling member connected to the housing. The coupling members can be carried from a disconnected to a connected position by a relative displacement between the foot and housing.
    Type: Grant
    Filed: April 25, 2001
    Date of Patent: March 16, 2004
    Assignee: Skil Europe B.V.
    Inventors: Brian Joseph Ellis, Eric Robert Larson, Stephen Michael Oshgan, Cornelis Johannes Maria Van Dun, Jan Peter Houben
  • Patent number: 6605981
    Abstract: An apparatus for biasing ultra-low voltage logic circuits is disclosed. An integrated circuit device includes multiple transistors and a global body bias circuit. The global body bias circuit includes a first transistor and second transistors connected in series between a power supply and a second power supply or ground. The gate and source of the first transistor are connected to the first power supply. The gate and source of the second transistor are connected to the second power supply. The drains and bodies of the first and second transistors are connected together to form an output connected to the bodies of the other transistors within the integrated circuit device.
    Type: Grant
    Filed: April 26, 2001
    Date of Patent: August 12, 2003
    Assignee: International Business Machines Corporation
    Inventors: Andres Bryant, Peter Edwin Cottrell, John Joseph Ellis-Monaghan, Mark B. Ketchen, Edward Joseph Nowak
  • Patent number: 6531379
    Abstract: The present invention employs a scanned atomic force probe to physical incorporate impurity atoms (dopant or bandgap) into a semiconductor substrate so that the impurity atoms have high resolution and improved placement. Specifically, the method of the present invention comprising a step of physically contacting a semiconductor surface having a layer of a dopant/bandgap source material thereon such that upon said physical contact impurity atoms from the dopant/bandgap source material are driven into the semiconductor substrate.
    Type: Grant
    Filed: April 9, 2001
    Date of Patent: March 11, 2003
    Assignee: International Business Machines Corporation
    Inventors: Toshiharu Furukawa, John Joseph Ellis-Monaghan, James Albert Slinkman
  • Publication number: 20020171468
    Abstract: An apparatus for biasing ultra-low voltage logic circuits is disclosed. An integrated circuit device includes multiple transistors and a global body bias circuit. The global body bias circuit includes a first transistor and second transistors connected in series between a power supply and a second power supply or ground. The gate and source of the first transistor are connected to the first power supply. The gate and source of the second transistor are connected to the second power supply. The drains and bodies of the first and second transistors are connected together to form an output connected to the bodies of the other transistors within the integrated circuit device.
    Type: Application
    Filed: April 26, 2001
    Publication date: November 21, 2002
    Applicant: International Business Machines Corporation
    Inventors: Andres Bryant, Peter Edwin Cottrell, John Joseph Ellis-Monaghan, Mark B. Ketchen, Edward Joseph Nowak
  • Publication number: 20020095798
    Abstract: An apparatus having a foot, a reciprocating saw and a housing. Between the foot and the housing there are means for releasable mounting the foot on the housing, characterized in that the releasable mounting means have a first coupling member connected to the foot and, co-acting therewith, a second coupling member connected to the housing. The coupling members can be carried from a disconnected to a connected position by a relative displacement between the foot and housing.
    Type: Application
    Filed: April 25, 2001
    Publication date: July 25, 2002
    Inventors: Brian Joseph Ellis, Eric Robert Larson, Stephen Michael Oshgan, Cornelis Johannes Maria Van Dun, Jan Peter Houben
  • Patent number: 6389075
    Abstract: A method and apparatus for digitally encoding video image data, which is particularly suited for encoding Internet Web pages, eliminates the need for performing time consuming, computationally intensive motion vector searches by taking advantage of prior knowledge regarding the Web page movement. In a first preferred embodiment, a digital video encoder, such as an MPEG encoder, employs Web page scrolling coordinates obtained from a browser application to determine, through calculation instead of searching, motion estimation for all the macroblocks of the present image frame relative to the previous frame. In a second preferred embodiment, the encoder receives information from the browser application that indicates that certain portions of an image, such as a Web page animation window, are continuously changing, and thus should be encoded as an intra frame.
    Type: Grant
    Filed: May 30, 2001
    Date of Patent: May 14, 2002
    Assignee: WorldGate Service, Inc.
    Inventors: Chuanming Wang, Bruce Plotnick, Joseph Ellis Augenbraun