Patents by Inventor Joseph F. Logan
Joseph F. Logan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150145710Abstract: Testing a digital-to-analog converter (DAC), where the test is carried out iteratively for a plurality of digital test signal values, includes: providing the digital test signal to a DAC under test and to a servo; providing, by the DAC under test to a summer, an analog test signal, including converting the digital test signal to the analog test signal; providing, by the summer to an observation latch, a summed signal, including summing the analog test signal and an analog offset signal, the analog offset signal received from a second DAC; providing, by the observation latch to the servo, a sample of the summed signal; providing, by the servo to the second DAC in dependence upon the sample and the digital test signal, a digital offset signal, where the second DAC converts the digital offset signal to the analog offset signal; and storing, as a digital observation, the digital offset signal.Type: ApplicationFiled: November 26, 2013Publication date: May 28, 2015Applicant: International Business Machines CorporationInventors: EUGENE R. ATWOOD, MATTHEW B. BAECHER, WILLIAM R. KELLY, JOSEPH F. LOGAN, PINPING SUN
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Patent number: 9041572Abstract: Testing a digital-to-analog converter (DAC), where the test is carried out iteratively for a plurality of digital test signal values, includes: providing the digital test signal to a DAC under test and to a servo; providing, by the DAC under test to a summer, an analog test signal, including converting the digital test signal to the analog test signal; providing, by the summer to an observation latch, a summed signal, including summing the analog test signal and an analog offset signal, the analog offset signal received from a second DAC; providing, by the observation latch to the servo, a sample of the summed signal; providing, by the servo to the second DAC in dependence upon the sample and the digital test signal, a digital offset signal, where the second DAC converts the digital offset signal to the analog offset signal; and storing, as a digital observation, the digital offset signal.Type: GrantFiled: November 26, 2013Date of Patent: May 26, 2015Assignee: International Business Machines CorporationInventors: Eugene R. Atwood, Matthew B. Baecher, William R. Kelly, Joseph F. Logan, Pinping Sun
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Patent number: 8169906Abstract: A method and system for managing asynchronous transfer mode (ATM) traffic in a computer system is disclosed. The computer system is used in sending, receiving, or sending and receiving a plurality of ATM flows. Each ATM flow has a plurality of ATM cells, a minimum ATM bandwidth guarantee, and a maximum ATM bandwidth. The method and system include determining whether excess bandwidth exists for the ATM flows. The method and system also include gracefully increasing a portion of the ATM cells transmitted for each ATM flow during periods of excess bandwidth. The portion of the ATM cells transmitted is not more than the maximum ATM bandwidth limit. If an ATM flow presents a sufficient offered load, the portion of the ATM cells transmitted in the flow is not less than a minimum ATM bandwidth guarantee.Type: GrantFiled: November 28, 2007Date of Patent: May 1, 2012Assignee: International Busines Machines CorporationInventors: Patrick Droz, Ilias Iliadis, Clark D. Jeffries, Andreas Kind, Joseph F. Logan
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Patent number: 7995472Abstract: A network processor dataflow chip and method for flexible dataflow are provided. The dataflow chip comprises a plurality of on-chip data transmission and scheduling circuit structures. The data transmission and scheduling circuit structures are selected responsive to indicators. Data transmission circuit structures may comprise selectable frame processing and data transmission functions. Selectable frame processing may comprise cut and paste, full dispatch and store and dispatch frame processing. Scheduling functions include full internal scheduling, calendar scheduling in communication with an external scheduler, and external calendar scheduling. In another aspect of the present invention, data transmission functions may comprise low latency and normal latency external processor interfaces for selectively providing privileged access to dataflow chip resources.Type: GrantFiled: January 6, 2009Date of Patent: August 9, 2011Assignee: International Business Machines CorporationInventors: Jean L. Calvignac, Chih-jen Chang, Joseph F. Logan, Fabrice J. Verplanken, Daniel Wind
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Patent number: 7643511Abstract: Packet switching node in a communication system includes apparatus for receiving incoming information packets or frames which contain header portions with formatting control blocks. Information in the frame's header contains frame alteration commands for modifying the information in the frame. The modifications include adding new information, deleting information, and overlaying information. Decoders and control devices in an alteration engine interpret the commands and apply the modifications to the frame data. Common and standard data patterns are stored for insertion or overlaying to conserve data packet space.Type: GrantFiled: December 3, 2008Date of Patent: January 5, 2010Assignee: International Business Machines CorporationInventors: Peter I. A. Barri, Claude Basso, Jean L. Calvignac, Brahmanand K. Gorti, Joseph F. Logan, Natarajan Valdhyanathan, Johan G. A. Verkinderen
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Publication number: 20090175275Abstract: A network processor dataflow chip and method for flexible dataflow are provided. The dataflow chip comprises a plurality of on-chip data transmission and scheduling circuit structures. The data transmission and scheduling circuit structures are selected responsive to indicators. Data transmission circuit structures may comprise selectable frame processing and data transmission functions. Selectable frame processing may comprise cut and paste, full dispatch and store and dispatch frame processing. Scheduling functions include full internal scheduling, calendar scheduling in communication with an external scheduler, and external calendar scheduling. In another aspect of the present invention, data transmission functions may comprise low latency and normal latency external processor interfaces for selectively providing privileged access to dataflow chip resources.Type: ApplicationFiled: January 6, 2009Publication date: July 9, 2009Applicant: International Business Machines CorporationInventors: Jean L. Calvignac, Chih-jen Chang, Joseph F. Logan, Fabrice J. Verplanken, Daniel Wind
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Publication number: 20090080461Abstract: Packet switching node in a communication system includes apparatus for receiving incoming information packets or frames which contain header portions with formatting control blocks. Information in the frame's header contains frame alteration commands for modifying the information in the frame. The modifications include adding new information, deleting information, and overlaying information. Decoders and control devices in an alteration engine interpret the commands and apply the modifications to the frame data. Common and standard data patterns are stored for insertion or overlaying to conserve data packet space.Type: ApplicationFiled: December 3, 2008Publication date: March 26, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: PETER I. A. BARRI, CLAUDE BASSO, JEAN L. CALVIGNAC, BRAHMANAND K. GORTI, JOSEPH F. LOGAN, NATARAJAN VALDHYANATHAN, JOHAN G. A. VERKINDEREN
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Patent number: 7483429Abstract: A network processor dataflow chip and method for flexible dataflow are provided. The dataflow chip comprises a plurality of on-chip data transmission and scheduling circuit structures. The data transmission and scheduling circuit structures are selected responsive to indicators. Data transmission circuit structures may comprise selectable frame processing and data transmission functions. Selectable frame processing may comprise cut and paste, full dispatch and store and dispatch frame processing. Scheduling functions include full internal scheduling, calendar scheduling in communication with an external scheduler, and external calendar scheduling. In another aspect of the present invention, data transmission functions may comprise low latency and normal latency external processor interfaces for selectively providing privileged access to dataflow chip resources.Type: GrantFiled: May 18, 2005Date of Patent: January 27, 2009Assignee: International Business Machines CorporationInventors: Jean L. Calvignac, Chih-jen Chang, Joseph F. Logan, Fabrice J. Verplanken, Daniel Wind
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Patent number: 7474672Abstract: Packet switching node in a communication system includes apparatus for receiving incoming information packets or frames which contain header portions with formatting control blocks. Information in the frame's header contains frame alteration commands for modifying the information in the frame. The modifications include adding new information, deleting information, and overlaying information. Decoders and control devices in an alteration engine interpret the commands and apply the modifications to the frame data. Common and standard data patterns are stored for insertion or overlaying to conserve data packet space.Type: GrantFiled: February 11, 2003Date of Patent: January 6, 2009Assignee: International Business Machines CorporationInventors: Peter I. A. Barri, Claude Basso, Jean L. Calvignac, Brahmanand K. Gorti, Joseph F. Logan, Natarajan Vaidhyanathan, Johan G. A. Verkinderen
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Patent number: 7466715Abstract: A communication network used to link information handling systems together utilizes a switching network to transmit data among senders and receivers. Each individual packet of data is described and controlled by an FCB. The bandwidth associated with the storing and distribution of data is optimized by chaining the data packets in different types of queues, or operating without chaining outside a queue. When a frame is in an output queue, the third word contains an RFCBA for egress of the frame to a line port, and an MCID for ingress from an output queue to a switch port. The RFCBA and the MCID have multicast capabilities. The format does not require a third word when a frame is in an input queue.Type: GrantFiled: March 28, 2005Date of Patent: December 16, 2008Assignee: International Business Machines CorporationInventors: Claude Basso, Jean L. Calvignac, Chih-jen Chang, Philippe Damon, Joseph F. Logan, Fabrice J. Verplanken
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Publication number: 20080285455Abstract: A medium and system for managing asynchronous transfer mode (ATM) traffic in a computer system is disclosed. The computer system is used in sending, receiving, or sending and receiving a plurality of ATM flows. Each ATM flow has a plurality of ATM cells, a minimum ATM bandwidth guarantee, and a maximum ATM bandwidth. The medium and system include determining whether excess bandwidth exists for the ATM flows. The method and system also include gracefully increasing a portion of the ATM cells transmitted for each ATM flow during periods of excess bandwidth. The portion of the ATM cells transmitted is not more than the maximum ATM bandwidth limit. If an ATM flow presents a sufficient offered load, the portion of the ATM cells transmitted in the flow is not less than a minimum ATM bandwidth guarantee.Type: ApplicationFiled: August 1, 2008Publication date: November 20, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Patrick DROZ, Ilias Iliadis, Clark D. Jeffries, Andreas Kind, Joseph F. Logan
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Patent number: 7317727Abstract: A method and system for managing asynchronous transfer mode (ATM) traffic in a computer system is disclosed. The computer system is used in sending, receiving, or sending and receiving a plurality of ATM flows. Each ATM flow has a plurality of ATM cells, a minimum ATM bandwidth guarantee, and a maximum ATM bandwidth. The method and system include determining whether excess bandwidth exists for the ATM flows. The method and system also include gracefully increasing a portion of the ATM cells transmitted for each ATM flow during periods of excess bandwidth. The portion of the ATM cells transmitted is not more than the maximum ATM bandwidth limit. If an ATM flow presents a sufficient offered load, the portion of the ATM cells transmitted in the flow is not less than a minimum ATM bandwidth guarantee.Type: GrantFiled: May 21, 2003Date of Patent: January 8, 2008Assignee: International Business Machines CorporationInventors: Patrick Droz, Ilias Iliadis, Clark D. Jeffries, Andreas Kind, Joseph F. Logan
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Publication number: 20040233912Abstract: A method and system for managing asynchronous transfer mode (ATM) traffic in a computer system is disclosed. The computer system is used in sending, receiving, or sending and receiving a plurality of ATM flows. Each ATM flow has a plurality of ATM cells, a minimum ATM bandwidth guarantee, and a maximum ATM bandwidth. The method and system include determining whether excess bandwidth exists for the ATM flows. The method and system also include gracefully increasing a portion of the ATM cells transmitted for each ATM flow during periods of excess bandwidth. The portion of the ATM cells transmitted is not more than the maximum ATM bandwidth limit. If an ATM flow presents a sufficient offered load, the portion of the ATM cells transmitted in the flow is not less than a minimum ATM bandwidth guarantee.Type: ApplicationFiled: May 21, 2003Publication date: November 25, 2004Applicant: International Business Machines CorporationInventors: Patrick Droz, Ilias Iliadis, Clark D. Jeffries, Andreas Kind, Joseph F. Logan
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Publication number: 20040156368Abstract: Packet switching node in a communication system includes apparatus for receiving incoming information packets or frames which contain header portions with formatting control blocks. Information in the frame's header contains frame alteration commands for modifying the information in the frame. The modifications include adding new information, deleting information, and overlaying information. Decoders and control devices in an alteration engine interpret the commands and apply the modifications to the frame data. Common and standard data patterns are stored for insertion or overlaying to conserve data packet space.Type: ApplicationFiled: February 11, 2003Publication date: August 12, 2004Applicants: International Business Machines Corporation, AlcatelInventors: Peter I. A. Barri, Claude Basso, Jean L. Calvignac, Brahmanand K. Gorti, Joseph F. Logan, Natarajan Vaidhyanathan, Johan G. A. Verkinderen
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Patent number: 6757795Abstract: A Network Processor (NP) includes a controller that allows maximum utilization of the memory. The controller includes a memory arbiter that monitors memory access requests from requesters in the NP and awards high priority requesters all the memory bandwidth requested per access to the memory. If the memory bandwidth requested by the high priority requester is less than the full memory bandwidth, the difference between the requested bandwidth and full memory bandwidth is assigned to lower priority requesters. By so doing every memory access utilizes the full memory bandwidth.Type: GrantFiled: February 5, 2002Date of Patent: June 29, 2004Assignees: International Business Machines Corporation, AlcatelInventors: Peter I. A. Barri, Jean L. Calvignac, Marco C. Heddes, Joseph F. Logan, Alex M. M. Niemegeers, Fabrice J. Verplanken, Miroslav Vrana
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Publication number: 20020141256Abstract: A Network Processor (NP) includes a controller that allows maximum utilization of the memory. The controller includes a memory arbiter that monitors memory access requests from requesters in the NP and awards high priority requesters all the memory bandwidth requested per access to the memory. If the memory bandwidth requested by the high priority requester is less than the full memory bandwidth, the difference between the requested bandwidth and full memory bandwidth is assigned to lower priority requesters. By so doing every memory access utilizes the full memory bandwidth.Type: ApplicationFiled: February 5, 2002Publication date: October 3, 2002Applicant: International Business Machines CorporationInventors: Peter I.A. Barri, Jean L. Calvignac, Marco C. Heddes, Joseph F. Logan, Alex M. M. Niemegeers, Fabrice J. Verplanken, Miroslav Vrana
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Patent number: 5608876Abstract: An adapter or add-in card for use in a peripheral component interconnect (PCI) computer includes a universal module which couples the card to the PCI bus. The module includes a set of selectively programmable configuration registers which are loaded by a microprocessor on the adapter. A circuit arrangement on the module issues a command which inhibits the PCI processor from accessing the configuration registers until fully loaded. Another circuit arrangement presents the Expansion ROM base address register as a `read/write` register or a read only register with all bits set to logical "0 " to the PCI computer. If the Expansion ROM base address register is presented as a read only register with all bits set to "0 ", the PCI computer concludes that no Expansion ROM exists on the add-in card, and its contents are not shadowed into the memory of the PCI computer. This disabling of the Expansion ROM causes memory space to be conserved in the computer.Type: GrantFiled: May 22, 1995Date of Patent: March 4, 1997Assignee: International Business Machines CorporationInventors: Ariel Cohen, William G. Holland, Joseph F. Logan, Avi Parash