Patents by Inventor Joseph F. Merlina

Joseph F. Merlina has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4236777
    Abstract: An integrated circuit package for establishing electrical contact with the terminal areas or pads of an integrated circuit chip comprises an insulating substrate having a flat surface in which there are embedded a plurality of electrodeposited conductors. The conductors have inner ends in a chip-receiving zone of the flat surface and have outer end portions which are remote from the chip-receiving zone. The inner ends of the conductors have contact bumps or promontories extending above the flat surface and located such that when a chip is placed on the promontories, they will be against the terminal areas of the chip. The chip can be held against the promontories by a suitable clamping means and contact established with the conductors at their outer ends by suitable connecting means. The device is particularly useful for testing chips prior to their being placed in service.
    Type: Grant
    Filed: July 27, 1979
    Date of Patent: December 2, 1980
    Assignee: AMP Incorporated
    Inventors: Joseph F. Merlina, John P. Redmond, George Ulbrich, Richard M. Wagner
  • Patent number: 4147889
    Abstract: An improved chip carrier of thin dieletric deformed into a dish configuration provided with flexible mounting flanges on which are plated or bonded solderable conductive traces and paths together with plated or bonded heat sinks which may be referenced to ground potential, and which provides structural integrity.
    Type: Grant
    Filed: February 28, 1978
    Date of Patent: April 3, 1979
    Assignee: AMP Incorporated
    Inventors: Daniel M. Andrews, Joseph F. Merlina, John P. Redmond, William S. Scheingold, George Ulbrich