Abstract: A processing system may include a plasma chamber operable to generate a plasma, and an extraction assembly, arranged along a side of the plasma chamber. The extraction assembly may include an extraction plate including an extraction aperture, the extraction plate having a non-planar shape, and generating an extracted ion beam at a high angle of incidence with respect to a perpendicular to a plane of a substrate, when the plane of the substrate is arranged parallel to the side of the plasma chamber.

Abstract: An apparatus for adjusting a microphone sampling rate, the apparatus including an input to receive an audio signal from a microphone and a front-end processing module. The front-end processing module is to generate a plurality of frames from the audio signal received by the microphone, determine a noise profile using the plurality of frames, and adjust a sampling rate of the microphone based on the determined noise profile.

Abstract: A sub-VT FPGA uses a low swing, dual-VDD interconnect scheme to reduce FPGA area per LUT, delay at a constant energy, and energy at a constant delay relative to a conventional design at low voltage. These improvements are made possible by a custom asynchronous sense amp, a separated voltage for memory cells, and an improved passgate interconnect to optimize routing delay with low energy overhead. This sub-threshold FPGA design enables energy efficient and cost effective configurable logic for a wide variety of ULP applications.

Abstract: An apparatus for adjusting a microphone sampling rate, the apparatus including an input to receive an audio signal from a microphone and a front-end processing module. The front-end processing module is to generate a plurality of frames from the audio signal received by the microphone, determine a noise profile using the plurality of frames, and adjust a sampling rate of the microphone based on the determined noise profile.

Abstract: A sub-VT FPGA uses a low swing, dual-VDD interconnect scheme to reduce FPGA area per LUT, delay at a constant energy, and energy at a constant delay relative to a conventional design at low voltage. These improvements are made possible by a custom asynchronous sense amp, a separated voltage for memory cells, and an improved passgate interconnect to optimize routing delay with low energy overhead. This sub-threshold FPGA design enables energy efficient and cost effective configurable logic for a wide variety of ULP applications.

Abstract: A system for enclosing an instrument, module or other assembly in an explosion-proof housing. The system includes an upper housing portion that includes a first threaded portion and, optionally, a transparent window portion; a lower housing portion that has a second threaded portion that is structured and arranged to cooperate with the first threaded portion to provide a tight, air- and water-tight fit; and an inner mounting assembly for supporting an instrument, module, electrical circuit, electrical device, display device, or other assembly. In pertinent part, the lower housing portion includes integrated bosses that provide horizontal surfaces for supporting the inner mounting assembly and for releasably attaching the inner mounting assembly to the lower housing portion.

Abstract: A system for enclosing an instrument, module or other assembly in an explosion-proof housing. The system includes an upper housing portion that includes a first threaded portion and, optionally, a transparent window portion; a lower housing portion that has a second threaded portion that is structured and arranged to cooperate with the first threaded portion to provide a tight, air- and water-tight fit; and an inner mounting assembly for supporting an instrument, module, electrical circuit, electrical device, display device, or other assembly. In pertinent part, the lower housing portion includes integrated bosses that provide horizontal surfaces for supporting the inner mounting assembly and for releasably attaching the inner mounting assembly to the lower housing portion.