Abstract: A carrier for a semiconductor component is provided having passive components integrated in its substrate. The passive components include decoupling components, such as capacitors and resistors. A set of connections is integrated to provide a close electrical proximity to the supported components.

Abstract: The present invention provides a high-performance metal-insulator-metal (MIM) capacitor which contains a high-k dielectric, yet no substantial shorting of the MIM capacitor is observed. Specifically, shorting of the MIM capacitor is substantially prevented in the present invention by forming a passivation layer between the high-k dielectric layer and each of the capacitor's electrodes. The inventive MIM capacitor includes a first conductor; a first passivation layer located atop the first conductor; a high-k dielectric layer located atop the first passivation layer; a second passivation layer located atop the high k dielectric layer; and a second conductor located atop the second passivation layer.

Abstract: Disclosed herein is a method, in an integrated, of forming a high-K node dielectric of a trench capacitor and a trench sidewall device dielectric at the same time. The method includes forming a trench in a single crystal layer of a semiconductor substrate, and forming an isolation collar along a portion of the trench sidewall, wherein the collar has a top below the top of the trench in the single crystal layer. Then, at the same time, a high-K dielectric is formed along the trench sidewall, the high-K dielectric extending in both an upper portion of the trench including above the isolation collar and in a lower portion of the trench below the isolation collar.

Abstract: A method and structure for a transistor device comprises forming a source, drain, and trench region in a substrate, forming a first insulator over the substrate, forming a gate electrode above the first insulator, forming a pair of insulating spacers adjoining the electrode, converting a portion of the first insulator into a metallic film, converting the metallic film into one of a silicide and a salicide film, forming an interconnect region above the trench region, forming an etch stop layer above the first insulator, the trench region, the gate electrode, and the pair of insulating spacers, forming a second insulator above the etch stop layer, and forming contacts in the second insulator. The first insulator comprises a metal oxide material, which comprises one of a HfOx and a ZrOx.

Abstract: A method and structure for a metal oxide semiconductor transistor having a substrate, a well region in the substrate, source and drain regions on opposite sides of the well region in the substrate, a gate insulator over the well region of the substrate, a polysilicon gate conductor over the gate insulator, and metallic spacers on sides of the gate conductor.

Abstract: A method and structure for a transistor device comprises forming a source, drain, and trench region in a substrate, forming a first insulator over the substrate, forming a gate electrode above the first insulator, forming a pair of insulating spacers adjoining the electrode, converting a portion of the first insulator into a metallic film, converting the metallic film into one of a silicide and a salicide film, forming an interconnect region above the trench region, forming an etch stop layer above the first insulator, the trench region, the gate electrode, and the pair of insulating spacers, forming a second insulator above the etch stop layer, and forming contacts in the second insulator. The first insulator comprises a metal oxide material, which comprises one of a HfOx and a ZrOx.

Abstract: A semiconductor device is fabricated using a micro-masking structure. The micro-masking structure is formed along the sidewalls of a trench in a semiconductor substrate or along the sidewalls of an electrode disposed over the semiconductor substrate. The micro-masking structure exposes portions of the sidewalls and covers other portions of the sidewalls. Then the exposed portions of the sidewalls are recessed to form a plurality of recesses such that the sidewalls have an increase surface area. After the recessing, the micro-masking structure is removed. The recessed sidewalls provide enhanced capacitance.

Abstract: A method and structure for an improved DRAM (dynamic random access memory) dielectric structure, whereby a new high-k material is implemented for both the support devices used as the gate dielectric as well as the capacitor dielectric. The method forms both deep isolated trench regions used for capacitor devices, and shallow isolated trench regions for support devices. The method also forms two different insulator layers, where one insulator layer with a uniform high-k dielectric constant is used for the deep trench regions and the support regions. The other insulator layer is used in the array regions in between the shallow trench regions.

Abstract: The present invention is a method and structure for fabricating a trench capacitor within a semiconductor substrate having a buried plate electrode formed of metal silicide. A collar is formed in a trench etched into a substrate; a conformal metal film is deposited thereover, and is annealed to form a silicide that is self-aligned to the collar. Silicide will not be formed on the collar, pads and other areas where the silicon is not directly exposed and hence the metal layer can be removed from these areas by selective etching.

Abstract: A method and structure for an integrated circuit structure that includes introducing precursors on a substrate, oxidizing the precursors and heating the precursors. The introducing and the oxidizing of the precursors is preformed in a manner so as to form an amorphous glass dielectric on the substrate. The process preferably includes, before introducing the precursors on the substrate, cleaning the substrate.

Abstract: A method and structure to form a conductive pattern on a ceramic sheet deposits a photosensitive conductive material on a carrier and exposes a pattern of x-ray energy on the material and sinters the carrier and the material to the ceramic sheet so that only the conductive pattern of the material remains on the ceramic sheet. The structure has a conductive patterned material which includes a photosensitive agent.

Abstract: A method and structure to form a conductive pattern on a ceramic sheet deposits a photosensitive conductive material on a carrier and exposes a pattern of x-ray energy on the material and sinters the carrier and the material to the ceramic sheet so that only the conductive pattern of the material remains on the ceramic sheet. The structure has a conductive patterned material which includes a photosensitive agent.

Abstract: Semiconductor devices having deep trenches with fill material therein having low resistivity are provided along with methods of fabricating such semiconductor devices.

Abstract: A method and structure for an improved DRAM (dynamic random access memory) dielectric structure, whereby a new high-k material is implemented for both the support devices used as the gate dielectric as well as the capacitor dielectric. The method forms both deep isolated trench regions used for capacitor devices, and shallow isolated trench regions for support devices. The method also forms two different insulator layers, where one insulator layer with a uniform high-k dielectric constant is used for the deep trench regions and the support regions. The other insulator layer is used in the array regions in between the shallow trench regions.

Abstract: A process of forming a high-k dielectric in an integrated circuit structure is disclosed. The process cleans a substrate to remove residual organic materials and strip native oxide from the surface of the substrate. Next, the process introduces precursors on the substrate in molar ratios consistent with formation of dielectric glass films. Following that, the process oxidizes the precursors, heats the precursors, and cools the precursors at a rate that avoids crystallization of the precursors.

Abstract: A method and structure for a metal oxide semiconductor field effect transistor (MOSFET) includes patterning a gate stack (having a gate conductor layer and a gate dielectric) over a substrate and modifying the gate dielectric beneath the gate conductor, such that the gate dielectric has a central portion and modified dielectric regions adjacent the central portion. The modified dielectric regions have a lower dielectric constant than that of the gate dielectric and the central portion is shorter than the gate conductor.

Abstract: A method and structure for simultaneously producing a dynamic random access memory device and associated transistor is disclosed. The method forms channel regions and capacitor openings in a substrate. Next, the invention deposits capacitor conductors in the capacitor openings. Then, the invention simultaneously forms a single insulator layer above the channel region and above the capacitor conductor. This single insulator layer comprises a capacitor node dielectric above the capacitor conductor and comprises a gate dielectric above the channel region.

Abstract: A low-temperature process for forming a highly conformal barrier film during integrated circuit manufacture by low pressure chemical vapor deposition (LPCVD). The process includes the following steps. First, the process provides ammonia and a silicon-containing gas selected from the group consisting of silane, dichlorosilane, bistertiarybutylaminosilanc, hexachlorodisilane, and mixtures of those compositions. The ratio of the volume of ammonia to the volume of the silicon-containing gas is adjusted to yield silicon concentrations greater than 43 atomic percent in the resultant film. The process applies a deposition temperature of 550° C. to 720° C. The ammonia and the silicon-containing gas are reacted at the deposition temperature to form a silicon-rich nitride film less than 200 Å thick. Finally, the silicon nitride film is deposited by low pressure chemical vapor deposition.