Patents by Inventor Joseph Farley
Joseph Farley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230389181Abstract: A bracket for holding a sensor at a location on a circuit board. The bracket comprises a main body and at least two leg members. Each leg member further includes a first end connected to the main body and a second end extending away from the main body at a predetermined angle. In an engaged position of the bracket, the second end of each leg member is configured to extend through a corresponding opening in the circuit board and wherein each second end further comprises a hook member configured to engage a bottom portion of the circuit board in the engaged of the bracket. The bracket further includes at least one spring member having a first surface configured to contact a top portion of the sensor and exert a force substantially normal to the circuit board in the engaged position of the bracket.Type: ApplicationFiled: October 6, 2021Publication date: November 30, 2023Inventors: Steven T. VARIEUR, Joseph FARLEY, John STOWELL
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Patent number: 11801334Abstract: The present invention discloses a sterile PRP separation kit that has compartmentalized container having a cover that allows for a stage-specific exposure of sterile components of the sterile PRP separation kit housed within stage-specific compartments to a non-sterile environment commensurate with a specific stage of operation of a separation process of PRP. The sterile PRP separation kit includes a PRP tube with segregated portals for injection of blood into the PRP tube, aspiration of PRP from the PRP tube, and for maintaining an interior pressure of the PRP tube at equilibrium with ambient pressure during both injection and aspiration.Type: GrantFiled: September 22, 2020Date of Patent: October 31, 2023Inventors: James Corey Orava, Patrick Joseph Farley
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Publication number: 20210085841Abstract: The present invention discloses a sterile PRP separation kit that has compartmentalized container having a cover that allows for a stage-specific exposure of sterile components of the sterile PRP separation kit housed within stage-specific compartments to a non-sterile environment commensurate with a specific stage of operation of a separation process of PRP. The sterile PRP separation kit includes a PRP tube with segregated portals for injection of blood into the PRP tube, aspiration of PRP from the PRP tube, and for maintaining an interior pressure of the PRP tube at equilibrium with ambient pressure during both injection and aspiration.Type: ApplicationFiled: September 22, 2020Publication date: March 25, 2021Applicant: Enso Discoveries, LLCInventors: James Corey Orava, Patrick Joseph Farley
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Publication number: 20070034026Abstract: A portable weathering test apparatus includes a portable housing, a specimen holder disposed in the housing and configured to hold at least one test specimen, a mounting board disposed in the housing at a distance from the specimen holder, an ultraviolet light source disposed on the mounting board and configured to emit ultraviolet radiation toward a testing surface of the specimen, and a power supply circuit operatively coupled to a power supply and the ultraviolet light source.Type: ApplicationFiled: August 10, 2005Publication date: February 15, 2007Applicant: ATLAS MATERIAL TESTING TECHNOLOGY, LLCInventors: Duncan Maciver, Joseph Farley
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Publication number: 20050169321Abstract: A fire alarm network fiber optic multiplex modem includes plural local interfaces, a fiber optic interface, a multiplexor, a fiber optic modem, and a demultiplexor. The multiplexor combines data received at the local interfaces into an outgoing data stream. The fiber optic modem transmits, at a first wavelength, the outgoing data stream to the fiber optic interface and receives, at a second wavelength, an incoming data stream via the fiber optic interface. The demultiplexor separates the incoming data stream into separate data streams, and forwards each of the separate data streams to its corresponding local interface.Type: ApplicationFiled: February 2, 2004Publication date: August 4, 2005Applicant: SimplexGrinnell LPInventors: Joseph Farley, Gary Vincent, Brian Rusiecki, Kenneth Savage
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Publication number: 20050145922Abstract: An EEPROM memory cell uses PMOS type floating gate transistor formed in a n-well, where the floating gate is routed over a p? diffused region formed in the n-well to form a control capacitor. The PMOS floating gate transistor uses a p-type diffused region below the p+ active region forming the drain to provide a higher breakdown voltage. Cell programming can be performed through hot-electron injection, with the electric field across the control capacitor to aid injection into the floating gate. FN erasure is achieved by taking the potential of the n-well to the programming voltage while holding the potential of the control capacitor at a low voltage.Type: ApplicationFiled: December 30, 2003Publication date: July 7, 2005Inventors: Joseph Farley, Jozef Mitros, Alec Morton, Robert Todd
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Patent number: 5875085Abstract: This device includes, connected in parallel with each of the elements (I, II), corresponding shunt regulators (S11, R11, S21, R21) linked together in series, and the control electrodes of which are connected to networks of resistors which represent voltages of the elements which can be applied to respective comparators (C11, C12, C21, C22) of the lower and upper threshold voltages (Vth11, Vth12, Vth21, Vth22) of the elements with a reference voltage delivered by a reference voltage source (Vref), a switching MOSFET transistor (4), with low conduction resistance and with defined off-state impedance, connected between the most negative terminal of the set of elements (II) in series and the negative terminal (Vbat-) of the protection device and means of control of the MOSFET transistor from output signals from the comparators (C11, C12, C21, C22) in order to alter the state of the said MOSFET transistor (4) for the purpose of regulating the state of charge and of discharge of the elements (I, II).Type: GrantFiled: February 23, 1996Date of Patent: February 23, 1999Assignee: Texas Instruments IncorporatedInventor: Joseph Farley
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Patent number: 5582928Abstract: The present invention relates to a supply battery arrangement having 3 terminals, for example a battery for a video camera recorder. This arrangement permits employing the battery both as an intelligent battery and as a non-intelligent battery capable of operating normally on devices of the standard video camera recorder type and also capable of communicating with a equipment or an intelligent device and displaying the state of charge with no additional terminals. The battery arrangement comprises a negative terminal (24) and a positive terminal (22) for supplying the equipment or the device with a voltage coming from the battery, a universal "T" terminal (26) operating as a thermal measuring means and a data terminal or a charge control output when it is employed by a computer, a charger or some other intelligent equipment or device.Type: GrantFiled: December 30, 1994Date of Patent: December 10, 1996Assignee: Texas Instruments IncorporatedInventor: Joseph Farley
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Patent number: 5545491Abstract: Battery pack arrangement having a control module 305 in the form of a programmed microcontroller and associated components on a printed circuit board, one or more battery cells 21 in which the respective cells are interconnected by metal conductive straps 22, wherein one of the interconnecting straps has a portion 309 of reduced width so as to serve as a current sensing element in conjunction with the control module 305. The reduced width of the interconnecting conductive strap 22 provides increased electrical resistance to the current flowing therein, with the value of the current sensing element 309 being measurable and storable in memory. The microcontroller and a regulating component of the control module are arranged to be located in intercellular space between successive cells in the cell array 21.Type: GrantFiled: June 1, 1994Date of Patent: August 13, 1996Assignee: Texas Instruments IncorporatedInventor: Joseph Farley