Abstract: A rigid flex circuit comprised of high thermal conductivity sections, said sections having components disposed so as to have their contacts substantially planar with the surface of the thermally conductive section and wherein the contacts are interconnected directly to the traces without the use of solder and further having the thermally conductive sections interconnected to one another by means of flexible circuit sections.

Abstract: A rigid flex circuit comprised of high thermal conductivity sections, said sections having components disposed so as to have their contacts substantially planar with the surface of the thermally conductive section and wherein the contacts are interconnected directly to the traces without the use of solder and further having the thermally conductive sections interconnected to one another by means of flexible circuit sections.

Abstract: A compliant layer is provided over a face of an undiced semiconductor wafer to form a portion of said compliant layer over each of a plurality of semiconductor chips integral with one another in the undiced wafer, each semiconductor chip having a plurality of contacts at its face. The compliant layer has a bottom surface adjacent the chip face, a top surface facing away from the bottom surface, and a sloping surface between the top and bottom surfaces. Bond ribbons of electrically conductive material are formed each extending from a contact of a respective semiconductor chip, along the sloping surface and the top surface of a portion of the compliant layer to a terminal supported by the top surface of the compliant layer. The packages are then separated from one another by dicing the wafer at semiconductor chip boundaries.

Abstract: A semiconductor chip package is fabricated including providing a compliant layer over a contact bearing face of a semiconductor chip, with a bottom surface of the compliant layer adjacent that chip face, a top surface facing away from the bottom surface, and at least one sloping surface extending between the top and bottom surfaces. Bond ribbons can be formed atop the compliant layer, each bond ribbon electrically coupling one of the contacts with an associated conductive terminal at the top surface of the compliant layer. A bond ribbon can include a strip extending along the sloping surface. The strip may have a substantially constant thickness in a direction away from the sloping surface.

Abstract: A method of making a semiconductor chip package is provided in which a compliant layer is provided over a contact bearing face of a semiconductor chip. The compliant layer can have a bottom surface adjacent to the chip face, a top surface facing away from the bottom surface, and at least one sloping surface between the top and bottom surfaces. The compliant layer can be disposed remote in a lateral direction along the contact bearing face from at least one contact adjacent to the sloping surface. Bond ribbons can be formed atop the compliant layer, wherein each bond ribbon electrically connects one of the contacts to an associated conductive terminal at the top surface of the compliant layer. The compliant layer can provide stress relief to the bond ribbons, such as during handling and affixing the assembly to an external substrate.

Abstract: A microelectronic unit can include a support structure including a dielectric having oppositely-directed first and second surfaces. A plurality of substantially rigid posts can protrude parallel to one another in a direction beyond the first surface of the support structure. Each post may have a top surface remote from the support structure, and the top surfaces can be substantially coplanar with one another. A microelectronic device having a surface with bond pads can overlie the second surface of the support structure with the bond pad-bearing surface of the microelectronic device facing toward the support structure. Connections can electrically connect the posts with the bond pads.

Abstract: A compliant semiconductor chip package assembly includes a semiconductor chip having a plurality of chip contacts, and a compliant layer having a top surface, a bottom surface and sloping peripheral edges, whereby the bottom surface of the compliant layer overlies a surface of the semiconductor chip. The assembly also includes a plurality of electrically conductive traces connected to the chip contacts of the semiconductor chip, the traces extending along the sloping edges to the top surface of the compliant layer. The assembly may include conductive terminals overlying the semiconductor chip, with the compliant layer supporting the conductive terminals over the semiconductor chip. The conductive traces have first ends electrically connected with the contacts of the semiconductor chip and second ends electrically connected with the conductive terminals. The conductive terminals are movable relative to the semiconductor chip.

Abstract: An LED lighting element comprised of at least two pieces designed for use with legacy lighting fixtures having a separable transformer and lighting element to improve efficacy and economy of LED lighting. In addition, the assembly can be provided with intelligent electronics for wireless control, operation and monitoring and/or with a battery for operation during power outages and/or as a warning system for the hearing impaired by stroboscopically flashing the LED lights and/or as sensing elements which cause activation due to some other sensed stimulus.

Abstract: A microelectronic assembly is provided which can include an element including a first dielectric layer and a second dielectric layer overlying the first dielectric layer, the second dielectric layer having an exposed surface defining an exposed major surface of the element. A plurality of substantially rigid metal posts can project beyond the exposed surface, the metal posts having ends remote from the exposed surface. The microelectronic assembly can include a microelectronic device which has bond pads and overlies the element. The microelectronic device can have a major surface which confronts the posts. Connections electrically connect the ends of the metal posts with the bond pads of the microelectronic device.

Abstract: A method of making a microelectronic connection component is disclosed. A plurality of portions of a conductive, etch-resistant material is provided on a surface of a metallic sheet. The sheet is etched from the surface to form posts extending generally parallel to one another aligned with the portions of the etch-resistant material. A microelectronic device is provided having one of a front face or a rear face overlying first ends of the posts. Second ends of the posts remote from the first ends face away from the microelectronic device as interconnection terminals for the connection component. At least some of the posts are electrically connected to the microelectronic device.

Abstract: A method of treating a component can include providing a component including a plurality of metallic posts extending generally parallel to one another. The providing step can be performed so that the posts have solder on the tips of the posts but not covering other portions of the posts. The method can include reflowing the solder provided on the posts so that the solder coats the posts. The providing step may be performed so that, prior to the reflowing step, the solder covers only the tips of the posts. The providing step can include depositing portions of the solder on a surface of a metallic sheet and etching the sheet from the surface. The plurality of posts may comprise elongated posts.

Abstract: A compliant semiconductor chip package assembly includes a semiconductor chip having a plurality of chip contacts, and a compliant layer having a top surface, a bottom surface and sloping peripheral edges, whereby the bottom surface of the compliant layer overlies a surface of the semiconductor chip. The assembly also includes a plurality of electrically conductive traces connected to the chip contacts of the semiconductor chip, the traces extending along the sloping edges to the top surface of the compliant layer. The assembly may include conductive terminals overlying the semiconductor chip, with the compliant layer supporting the conductive terminals over the semiconductor chip. The conductive traces have first ends electrically connected with the contacts of the semiconductor chip and second ends electrically connected with the conductive terminals. The conductive terminals are movable relative to the semiconductor chip.

Abstract: A compliant semiconductor chip package assembly includes a a semiconductor chip having a plurality of chip contacts, and a compliant layer having a top surface, a bottom surface and sloping peripheral edges, whereby the bottom surface of the compliant layer overlies a surface of the semiconductor chip. The assembly also includes a plurality of electrically conductive traces connected to the chip contacts of the semiconductor chip, the traces extending along the sloping edges to the top surface of the compliant layer. The assembly may include conductive terminals overlying the semiconductor chip, with the compliant layer supporting the conductive terminals over the semiconductor chip. The conductive traces have first ends electrically connected with the contacts of the semiconductor chip and second ends electrically connected with the conductive terminals. The conductive terminals are movable relative to the semiconductor chip.

Abstract: A method of making a semiconductor chip package is provided in which a compliant layer is provided over a contact bearing face of a semiconductor chip. The compliant layer can have a bottom surface adjacent to the chip face, a top surface facing away from the bottom surface, and at least one sloping surface between the top and bottom surfaces. The compliant layer can be disposed remote in a lateral direction along the contact bearing face from at least one contact adjacent to the sloping surface. Bond ribbons can be formed atop the compliant layer, wherein each bond ribbon electrically connects one of the contacts to an associated conductive terminal at the top surface of the compliant layer. The compliant layer can provide stress relief to the bond ribbons, such as during handling and affixing the assembly to an external substrate.

Abstract: A method of treating a component can include providing a component including a plurality of metallic posts extending generally parallel to one another. The providing step can be performed so that the posts have solder on the tips of the posts but not covering other portions of the posts. The method can include reflowing the solder provided on the posts so that the solder coats the posts. The providing step may be performed so that, prior to the reflowing step, the solder covers only the tips of the posts. The providing step can include depositing portions of the solder on a surface of a metallic sheet and etching the sheet from the surface. The plurality of posts may comprise elongated posts.

Abstract: A microelectronic unit can include a support structure including a dielectric having oppositely-directed first and second surfaces. A plurality of substantially rigid posts can protrude parallel to one another in a direction beyond the first surface of the support structure. Each post may have a top surface remote from the support structure, and the top surfaces can be substantially coplanar with one another. A microelectronic device having a surface with bond pads can overlie the second surface of the support structure with the bond pad-bearing surface of the microelectronic device facing toward the support structure. Connections can electrically connect the posts with the bond pads.

Abstract: A microelectronic assembly is provided which can include an element including a first dielectric layer and a second dielectric layer overlying the first dielectric layer, the second dielectric layer having an exposed surface defining an exposed major surface of the element. A plurality of substantially rigid metal posts can project beyond the exposed surface, the metal posts having ends remote from the exposed surface. The microelectronic assembly can include a microelectronic device which has bond pads and overlies the element. The microelectronic device can have a major surface which confronts the posts. Connections electrically connect the ends of the metal posts with the bond pads of the microelectronic device.

Abstract: A method of electrically connecting a microelectronic component having a first surface bearing a plurality of contacts. The method including the steps of forming a subassembly by juxtaposing a connection component having a support structure and a plurality of elongated posts extending substantially parallel to one another from a first surface of the support structure with the microelectronic component so that the support structure overlies the surface of the component with the posts extending away from the component and electrically connecting the posts to the contacts of the microelectronic component.

Abstract: A method of providing a substantially void free layer for one or more flip chip assemblies, or one or more microelectronic components, utilizing a curable encapsulant. Also disclosed is a method of injecting an encapsulant into an assembly and a method of treating a microelectronic component to form a void free layer.