Patents by Inventor Joseph Francis ROHLMAN

Joseph Francis ROHLMAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Low-power static random access memory
    Patent number: 11955170
    Abstract: A static random-access memory is set forth comprising: a word line circuit for generating a word line signal on a word line; a plurality of six-transistor memory cells arranged between a first bitline, a second bitline and the word line for simultaneously selecting one of either all or a portion of the plurality of six-transistor memory cells for data reading or writing, and wherein each memory cell includes first and second n-channel transistors and a bitline precharge circuit for precharging the first bitline and second bitline to a voltage of Vdd/2 prior to the first and second n-channel transistors receiving the word line signal.
    Type: Grant
    Filed: August 21, 2023
    Date of Patent: April 9, 2024
    Assignee: UNTETHER AI CORPORATION
    Inventors: Katsuyuki Sato, William Martin Snelgrove, Saijagan Saijagan, Joseph Francis Rohlman
  • LOW-POWER STATIC RANDOM ACCESS MEMORY
    Publication number: 20240021237
    Abstract: A static random-access memory is set forth comprising: a word line circuit for generating a word line signal on a word line; a plurality of six-transistor memory cells arranged between a first bitline, a second bitline and the word line for simultaneously selecting one of either all or a portion of the plurality of six-transistor memory cells for data reading or writing, and wherein each memory cell includes first and second n-channel transistors and a bitline precharge circuit for precharging the first bitline and second bitline to a voltage of Vdd/2 prior to the first and second n-channel transistors receiving the word line signal.
    Type: Application
    Filed: June 21, 2022
    Publication date: January 18, 2024
    Inventors: Katsuyuki SATO, William Martin SNELGROVE, Saijagan SAIJAGAN, Joseph Francis ROHLMAN
  • LOW-POWER STATIC RANDOM ACCESS MEMORY
    Publication number: 20230420040
    Abstract: A static random-access memory is set forth comprising: a word line circuit for generating a word line signal on a word line; a plurality of six-transistor memory cells arranged between a first bitline, a second bitline and the word line for simultaneously selecting one of either all or a portion of the plurality of six-transistor memory cells for data reading or writing, and wherein each memory cell includes first and second n-channel transistors and a bitline precharge circuit for precharging the first bitline and second bitline to a voltage of Vdd/2 prior to the first and second n-channel transistors receiving the word line signal.
    Type: Application
    Filed: August 21, 2023
    Publication date: December 28, 2023
    Inventors: Katsuyuki SATO, William Martin SNELGROVE, Saijagan SAIJAGAN, Joseph Francis ROHLMAN