Abstract: A method of forming a nitrided silicon oxide layer. The method includes: forming a silicon dioxide layer on a surface of a silicon substrate; performing a rapid thermal nitridation of the silicon dioxide layer at a temperature of less than or equal to about 900° C. and a pressure greater than about 500 Torr to form an initial nitrided silicon oxide layer; and performing a rapid thermal oxidation or anneal of the initial nitrided silicon oxide layer at a temperature of less than or equal to about 900° C. and a pressure greater than about 500 Torr to form a nitrided silicon oxide layer. Also a method of forming a MOSFET with a nitrided silicon oxide dielectric layer.

Abstract: A method of forming a nitrided silicon oxide layer. The method includes: forming a silicon dioxide layer on a surface of a silicon substrate; performing a rapid thermal nitridation of the silicon dioxide layer at a temperature of less than or equal to about 900° C. and a pressure greater than about 500 Torr to form an initial nitrided silicon oxide layer; and performing a rapid thermal oxidation or anneal of the initial nitrided silicon oxide layer at a temperature of less than or equal to about 900° C. and a pressure greater than about 500 Torr to form a nitrided silicon oxide layer. Also a method of forming a MOSFET with a nitrided silicon oxide dielectric layer.

Abstract: An integrated circuit using high-performance bipolar and CMOS transistor elements on a single chip is fabricated by a simplified process requiring minimal, if any, changes in the process used for forming either type of device in accordance with a variety of possible device designs. The method according to the invention makes maximal use of self-aligned and self-masking processes to reduce the number of processing steps. The number of processing steps is further reduced by performing some steps concurrently on different device types. Further, the masking steps which are employed are reasonably misregistration tolerant, resulting in high manufacturing yield for the process. Consequently, the process according to the invention substantially eliminates the existence of trade-offs between element performance, integration density and process complexity and cost when plural technologies are integrated on the same chip.

Abstract: Improved packing density as well as improved performance and manufacturing yield is achieved in an electrically programmable memory by confining floating gate structures between isolation structures covered with a thin nitride layer. The confinement of the floating gate is achieved by planarization, preferably with a self-limiting chemical/mechanical polishing process, to the surface of the nitride layer covering the isolation structures. Gate oxide and control electrode connections can then be formed on a substantially planar surface without compromising the quality of the gate oxide or breakdown voltage the device must withstand for programming. Since severe topology is avoided over which these connections are formed, improved formation of low resistance connections, possibly including metal connections, are possible and allow scaling of transistors of the memory cells to be scaled to sizes not previously possible.

Abstract: A simple method of making a thin film transistor (TFT) on a substrate with an insulating surface layer is disclosed. A layer of dopant source layer is deposited on the insulating layer, followed by defining a gate stack consisting of a gate polysilicon, gate insulator and a protective polysilicon using the dopant source layer as an etch stop. Sidewall spacers are formed in contact with the gate stack. A TFT body polysilicon is deposited and patterned, forming thereby the source and drain regions in a self-aligned manner. By heating, the dopants from the dopant source layer are driven into the source/drain and to part of the off-set regions of the body polysilicon layer while simultaneously also doping the gate polysilicon.

Abstract: A method of gettering an SOI wafer from the front side of the wafer includes depositing a gettering layer, such as polysilicon, on the SOI layer and annealing the SOI wafer with the gettering layer in place. A polish stop structure, which can be deposited before or after the gettering layer, provides a means for selectively removing the gettering layer from the SOI wafer without damaging the surface or eroding the thickness of the SOI layer.

Abstract: Improved packing density as well as improved performance and manufacturing yield is achieved in an electrically programmable memory by confining floating gate structures between isolation structures covered with a thin nitride layer. The confinement of the floating gate is achieved by planarization, preferably with a self-limiting chemical/mechanical polishing process, to the surface of the nitride layer covering the isolation structures. Gate oxide and control electrode connections can then be formed on a substantially planar surface without compromising the quality of the gate oxide or breakdown voltage the device must withstand for programming. Since severe topology is avoided over which these connections are formed, improved formation of low resistance connections, possibly including metal connections, are possible and allow scaling of transistors of the memory cells to be scaled to sizes not previously possible.