Abstract: A base substrate, high-k substrate layers on the base substrate with discrete decoupling capacitors embedded, high density substrate layers on the high-k substrate layers supporting wiring and wiring spacing of less than 2 up to about 10 micron width, pitch connectivity between the upper surface of the base substrate and a lower surface of the set of high density substrate layers supports less than 50 up to about 300 micron pitch, the pitch connectivity on an upper surface of the set of high density substrate layers supports less than about 150 micron pitch. A method including attaching a set of metal posts at each contact on a lower surface of a set of high density substrate layers, attaching to a handler, attaching an interconnect layer to a base substrate, and attaching the set of high density substrate layers to the base substrate while aligning each metal post with a contact.

Abstract: The present disclosure relates to a photovoltaic (PV) device that includes a first junction constructed with a first alloy and having a bandgap between about 1.0 eV and about 1.5 eV, and a second junction constructed with a second alloy and having a bandgap between about 0.9 eV and about 1.3 eV, where the first alloy includes III-V elements, the second alloy includes III-V elements, and the PV device is configured to operate in a thermophotovoltaic system having an operating temperature between about 1500° C. and about 3000° C.

Abstract: A current mode end-to-end signal path includes, a digital to analog converter (DAC), operating in current mode and an upconverting mixer, operating in current mode and operatively coupled to the DAC, wherein analog inputs and analog outputs of the DAC and the upconverting mixer are represented as currents, and the DAC generates a baseband signal.

Abstract: The present disclosure relates to a photovoltaic (PV) device that includes a first junction constructed with a first alloy and having a bandgap between about 1.0 eV and about 1.5 eV, and a second junction constructed with a second alloy and having a bandgap between about 0.9 eV and about 1.3 eV, where the first alloy includes III-V elements, the second alloy includes III-V elements, and the PV device is configured to operate in a thermophotovoltaic system having an operating temperature between about 1500° C. and about 3000° C.

Abstract: A variable capacitor device comprises first and second control paths which are configured to enable differential control using first and second transistors of a same doping type in the first and second control paths, respectively, wherein the first and second transistors are configured as voltage variable resistors for tuning a capacitance of the variable capacitor device.

Abstract: A variable capacitor device comprises first and second control paths which are configured to enable differential control using first and second transistors of a same doping type in the first and second control paths, respectively, wherein the first and second transistors are configured as voltage variable resistors for tuning a capacitance of the variable capacitor device.

Abstract: The present disclosure relates to a photovoltaic (PV) device that includes a first junction constructed with a first alloy and having a bandgap between about 1.0 eV and about 1.5 eV, and a second junction constructed with a second alloy and having a bandgap between about 0.9 eV and about 1.3 eV, where the first alloy includes III-V elements, the second alloy includes III-V elements, and the PV device is configured to operate in a thermophotovoltaic system having an operating temperature between about 1500° C. and about 3000° C.

Abstract: A device comprises a voltage-mode filter circuit, a current-mode output circuit, and a regulation circuit. The voltage-mode filter circuit is configured to generate a voltage signal on an output terminal thereof. The current-mode output circuit comprises an input transistor which comprises a gate terminal coupled to the output terminal of the voltage-mode filter circuit, and a source terminal coupled to a regulated node. The regulation circuit is configured to adjust a voltage level on the regulated node to maintain a constant gate-source bias voltage for the input transistor to generate a current for biasing the current-mode output circuit.

Abstract: The present disclosure relates to a method for manufacturing a device, where the device includes, in order, a metamorphic contact layer, a first metamorphic junction, a metamorphic tunnel junction, and a second metamorphic junction. To produce the device, the manufacturing includes, in order, a first depositing of a buffer layer onto a substrate, a second depositing of the metamorphic contact layer, a third depositing of the first metamorphic junction, a fourth depositing of the metamorphic tunnel junction, a fifth depositing of the second metamorphic junction, and the removing of the buffer layer and the substrate.

Abstract: Techniques are provided for calibrating signal currents in a radio frequency signal generator system, such as an arbitrary waveform generator system. A device comprises a current measurement circuit and a current imbalance correction circuit. The current measurement circuit is configured, during a calibration process, to measure a first current in a first signal path of a radio frequency signal generator, and to measure a second current in a second signal path of the radio frequency signal generator. The current imbalance correction circuit is configured to adjust a current level in at least one of the first signal path and the second signal path of the radio frequency signal generator to correct for an imbalance between the measured first current and the measured second current.

Abstract: Disclosed herein are devices, systems and methods useful for downhole sensors and electronics suitable for harsh thermal and mechanical environment associated with high-temperature geothermal drilling and high-temperature/high-pressure oil and gas drilling.

Abstract: A base substrate, high-k substrate layers on the base substrate with discrete decoupling capacitors embedded, high density substrate layers on the high-k substrate layers supporting wiring and wiring spacing of less than 2 up to about 10 micron width, pitch connectivity between the upper surface of the base substrate and a lower surface of the set of high density substrate layers supports less than 50 up to about 300 micron pitch, the pitch connectivity on an upper surface of the set of high density substrate layers supports less than about 150 micron pitch. A method including attaching a set of metal posts at each contact on a lower surface of a set of high density substrate layers, attaching to a handler, attaching an interconnect layer to a base substrate, and attaching the set of high density substrate layers to the base substrate while aligning each metal post with a contact.

Abstract: A current mode end-to-end signal path includes, a digital to analog converter (DAC), operating in current mode and an upconverting mixer, operating in current mode and operatively coupled to the DAC, wherein analog inputs and analog outputs of the DAC and the upconverting mixer are represented as currents, and the DAC generates a baseband signal.

Abstract: A method (and structure) includes receiving a challenge for an authentication, in a chip having stored in a memory device therein a secret to be used in an authentication attempt of the chip by an external agent. The chip includes a hardware processing circuit to sequentially perform a processing related to the secret. The secret is retrieved from the memory device and processed in the hardware processing circuit in accordance with information included in the received challenge. The result of the processing in the hardware processing circuit is transmitted as a response to the challenge. The hardware processing circuit executes in a parallel manner, thereby reducing a signal that can be detected by an adversary attempting a side channel attack to secure the secret.

Abstract: The present disclosure relates to a photovoltaic (PV) device that includes a first junction constructed with a first alloy and having a bandgap between about 1.0 eV and about 1.5 eV, and a second junction constructed with a second alloy and having a bandgap between about 0.9 eV and about 1.3 eV, where the first alloy includes III-V elements, the second alloy includes III-V elements, and the PV device is configured to operate in a thermophotovoltaic system having an operating temperature between about 1500° C. and about 3000° C.

Abstract: An example operation may include one or more of receiving, via a network, tag data that is read from a tag associated with a physical object and signed with a key assigned to the tag, determining, via a blockchain peer, that the signed tag data is validly signed based on a corresponding key pair of the tag which is accessible to the blockchain peer, determining, via the blockchain peer, whether the tag data satisfies of one or more predefined conditions of the physical object, and storing the determination via a blockchain database.

Abstract: The present disclosure relates to a photovoltaic (PV) device that includes a first junction constructed with a first alloy and having a bandgap between about 1.0 eV and about 1.5 eV, and a second junction constructed with a second alloy and having a bandgap between about 0.9 eV and about 1.3 eV, where the first alloy includes III-V elements, the second alloy includes III-V elements, and the PV device is configured to operate in a thermophotovoltaic system having an operating temperature between about 1500° C. and about 3000° C.

Abstract: A single flux quantum (SFQ) circuit includes a radio frequency (RF) to direct current (DC) conversion stage. A DC to RF current conversion stage is coupled to a single output of the RF to DC conversion stage. The DC to RF current conversion stage includes a plurality of series stacked Josephson Junctions (JJs) having n stages, configured to convert a DC current received from the RF to DC conversion stage and reconvert the DC current to an RF tone.

Abstract: The present disclosure relates to a method for manufacturing a device, where the device includes, in order, a metamorphic contact layer, a first metamorphic junction, a metamorphic tunnel junction, and a second metamorphic junction. To produce the device, the manufacturing includes, in order, a first depositing of a buffer layer onto a substrate, a second depositing of the metamorphic contact layer, a third depositing of the first metamorphic junction, a fourth depositing of the metamorphic tunnel junction, a fifth depositing of the second metamorphic junction, and the removing of the buffer layer and the substrate.

Abstract: Devices, computer-implemented methods, and systems that can facilitate radio frequency identification components are provided. According to an embodiment, a device can comprise a memory that can be coupled to an integrated circuit device that can have a processor and an accelerator component that can execute a cryptographic module. The device can further comprise a radio frequency identification device that can be coupled to the integrated circuit device that can communicate with a radio frequency identification reader device based on the cryptographic module.