Abstract: A method of implementing pulse-width modulation in a display system (10, 20) that uses a spatial light modulator (SLM) (15) Each frame of data is divided into bit-planes, each bit-plane having one bit of data for each pixel of the SLM and representing a bit weight of the intensity value to be displayed by the pixels. Each bit-plane has a display time corresponding to a portion of the frame period, with bit-planes of more significant bits having longer portions. Then, the display times for one or more of the more significant bits are segmented so that the data for those bits can be displayed in segments rather than for a continuous time. (FIG. 3A). The segments are distributed throughout the frame period to reduce visual artifacts. (FIG. 3B).

Abstract: A digital motor controller (17) for controlling both the phase and speed of a brushless DC motor (16). An error detection unit (21) detects a speed error or a phase error. An error logic unit (22) uses the error to determine a speed control value, that is proportional to represent an average motor input voltage that varies from the current input voltage by an amount determined by the error. A pulse width modulation unit (23) receives the speed control value and uses it to determine the duty cycle for the motor drive signals. A commutation unit (24) modulates the appropriate drive signal, and a drive stage (27) delivers the drive signals to the motor (16).

Abstract: A system (30) for packing data into a video processor is provided. System (30) comprises demultiplexer (32), first and second first in-first out buffer memories (34) and (36), and multiplexer (38). Demultiplexer (32) divides a field of video data into first and second parts (42) and (44). First and second parts (42) and (44) are stored in first first in-first out buffer memories (34) and (36), respectively. Multiplexer (38) combines one line from first first in-first out buffer memory (34) with one line from second first in-first out buffer memory (36) to form a single line for processing.

Abstract: A sequential color system is provided in which a processor (22) is coupled to a memory (24) and a receiver (27). Images are generated by shining light from a light source (28) through a color wheel (30) and onto DMD array (26). Light from the DMD array (26) is shone on screen (32). By adjusting the speed and make-up of color wheel (30) color separation is greatly reduced or eliminated. Also there are techniques for sequential imaging which may be applied to other technologies, such as CRT technologies.