Patents by Inventor Joseph G. Renauer

Joseph G. Renauer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160233772
    Abstract: A power regulator for converting an input voltage to an output voltage includes and inductor, wherein the output voltage of the regulator is in response to charging of the inductor at a clock frequency. An error amplifier has an inverting input coupled to the regulator output, and a non-inverting input coupled to a reference voltage. A slope compensation circuit is for generating a signal for charging the inductor. The compensation circuit includes an output coupled the circuitry for charging the inductor, wherein a signal on the output is generated in response to the input voltage, the output voltage, and the clock frequency.
    Type: Application
    Filed: December 31, 2015
    Publication date: August 11, 2016
    Inventors: Joseph G. Renauer, Joel N. Brassfield
  • Patent number: 6222745
    Abstract: A DC to DC converter includes multiple stages to share power handling. The stages are connected in parallel paths between the source input and the load output of the power converter. An analog error signal is generated by comparing the load output signal to a reference signal. The error signal is fed to a phase shifting input of a phase lock loop. The phase lock loop is connected to receive a reference clock signal and maintain a relative clock signal shifted in phase from the reference clock signal by an amount depending on the error signal. Digital divider circuits and digital logic circuits are used to produce phase shifted variable pulse width control signals for the stages. The parallel connected power conversion stages equally share the transfer of power from the input source to an output load. A single analog to digital conversion of a single analog error signal to multiple, phase shifted, variable duty cycle clocks is provided.
    Type: Grant
    Filed: October 19, 1999
    Date of Patent: April 24, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Michael G. Amaro, Joseph G. Renauer
  • Patent number: 5883797
    Abstract: A power conversion architecture includes one control capable of simultaneous operation with multiple power conversion circuits. The function of the controlling mechanism includes an output signal proportional to one or more inputs to the controlling mechanism for the purpose of maintaining a destination level at a substantially constant value. The function of each power conversion path is to transfer power from a source to a destination in an amount dictated by the controlling mechanism. The function of the parallel power conversion architecture is to proportionally distribute the power transfer between all power conversion paths.
    Type: Grant
    Filed: June 30, 1997
    Date of Patent: March 16, 1999
    Assignee: Power Trends, Inc.
    Inventors: Michael G. Amaro, Joseph G. Renauer