Patents by Inventor Joseph Gerald McDonald

Joseph Gerald McDonald has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6073181
    Abstract: A LAN adapter for transferring data frames from a LAN to memory buffers in a processor in which the LAN driver follows either the ODI or the NDIS specification. The adapter accumulates the frame length and compares this to the storage capacity of the buffer. If the frame length does not exceed the buffer capacity and the LAN driver implements the ODI specification, the adapter will indicate good status to the driver. If the frame length exceeds the buffer capacity the adapter will either send bad status to the ODI driver or reuse the buffer and send no status. If the driver follows NDIS, status is sent at the end of the frame.
    Type: Grant
    Filed: June 3, 1997
    Date of Patent: June 6, 2000
    Assignee: International Business Machines Corporation
    Inventors: William G. Holland, Joseph Franklin Logan, Joseph Gerald McDonald, Gregory Francis Paussa
  • Patent number: 6049842
    Abstract: A method for transferring data between non-contiguous buffers in a memory and an I/O device via a system I/O bus uses a descriptor queue stored in memory. Each descriptor points to a buffer and includes the length of the buffer. The I/O device is provided with the base address of the queue, the length of the queue and a current address which at initialization is the same as the base address. When data is to be transferred a device driver located in the processor sends the number of available descriptors (DescrEnq) to the I/O device which accesses the descriptors individually or in burst mode to gain access to the data buffers identified by the descriptors.
    Type: Grant
    Filed: May 1, 1997
    Date of Patent: April 11, 2000
    Assignee: International Business Machines Corporation
    Inventors: Henry Michael Garrett, William G. Holland, Joseph Franklin Logan, Joseph Gerald McDonald, John Kenneth Stacy
  • Patent number: 5905913
    Abstract: An interrupt mechanism associated with a peripheral devise is connected to a processor by an interrupt driven I/O bus. The mechanism includes an n input System Interrupt Status Register (SISR) which collects up to n different interrupts from the device during a predetermined time period. Gate and timing circuits under control of signals provided by the processor regulate the frequency of the interrupts thus reducing the number of interrupt operations required to service the device.
    Type: Grant
    Filed: April 24, 1997
    Date of Patent: May 18, 1999
    Assignee: International Business Machines Corporation
    Inventors: Henry Michael Garrett, William G. Holland, Joseph Franklin Logan, Joseph Gerald McDonald