Patents by Inventor Joseph Gredone

Joseph Gredone has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10153870
    Abstract: A method and apparatus for operating supplementary cells in licensed exempt (LE) spectrum. An aggregating cell operating in a frequency division duplex (FDD) licensed spectrum is aggregated with a LE supplementary cell operating in a time sharing mode for uplink (UL) and downlink (DL) operations. The LE supplementary cell may be an FDD supplementary cell dynamically configurable between an UL only mode, a DL only mode, and a shared mode, to match requested UL and DL traffic ratios. The LE supplementary cell may be a time division duplex (TDD) supplementary cell. The TDD supplementary cell may be dynamically configurable between multiple TDD configurations. A coexistence capability for coordinating operations between the LE supplementary cell with other systems operating in the same channel is provided. Coexistence gaps are provided to measure primary/secondary user usage and permit other systems operating in the LE supplementary cell channel to access the channel.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: December 11, 2018
    Assignee: InterDigital Patent Holdongs, Inc.
    Inventors: Jean-Louis Gauvreau, Martino M. Freda, Zinan Lin, Joseph M. Murray, Chunxuan Ye, Erdem Bala, Mihaela C. Beluri, Douglas R. Castor, Amith V. Chincholi, Angelo A. Cuffaro, Yuying Dai, Alpaslan Demir, Joseph Gredone, Rui Yang, Liangping Ma, Rocco Di Girolamo, Debashish Purkayastha, Athmane Touag
  • Publication number: 20180152268
    Abstract: A method and apparatus for operating supplementary cells in licensed exempt (LE) spectrum. An aggregating cell operating in a frequency division duplex (FDD) licensed spectrum is aggregated with a LE supplementary cell operating in a time sharing mode for uplink (UL) and downlink (DL) operations. The LE supplementary cell may be an FDD supplementary cell dynamically configurable between an UL only mode, a DL only mode, and a shared mode, to match requested UL and DL traffic ratios. The LE supplementary cell may be a time division duplex (TDD) supplementary cell. The TDD supplementary cell may be dynamically configurable between multiple TDD configurations. A coexistence capability for coordinating operations between the LE supplementary cell with other systems operating in the same channel is provided. Coexistence gaps are provided to measure primary/secondary user usage and permit other systems operating in the LE supplementary cell channel to access the channel.
    Type: Application
    Filed: January 29, 2018
    Publication date: May 31, 2018
    Applicant: InterDigital Patent Holdings, Inc.
    Inventors: Jean-Louis Gauvreau, Martino M. Freda, Zinan Lin, Joseph M. Murray, Chunxuan Ye, Erdem Bala, Mihaela C. Beluri, Douglas R. Castor, Amith V. Chincholi, Angelo A. Cuffaro, Yuying Dai, Alpaslan Demir, Joseph Gredone, Rui Yang, Liangping Ma, Rocco Di Girolamo, Debashish Purkayastha, Athmane Touag
  • Publication number: 20180131687
    Abstract: A certification provenance tree (CPT) structure may provide information concerning a layered certification of a device that comprises a hierarchy of components. The CPT structure may include a hierarchy of secure certification provenance document (SCPD) structures. Each SCPD structure in the hierarchy may represent a given component at a given level of the hierarchy of components of the device. Each SCPD structure may include a field that stores a certification proof indicating that security properties of the given component have been certified by a certification authority. An SCPD structure may further include accreditation information fields that store a pointer to an SCPD structure of a component at a next layer of the hierarchy of components of the device. The pointer may provide an indication of assurance that the component at that next layer will perform securely within this component at said given layer.
    Type: Application
    Filed: September 1, 2017
    Publication date: May 10, 2018
    Inventors: Dolores F. Howry, Yogendra C. Shah, Alec Brusilovsky, Joseph Gredone
  • Patent number: 9882684
    Abstract: A method and apparatus for operating supplementary cells in licensed exempt (LE) spectrum. An aggregating cell operating in a frequency division duplex (FDD) licensed spectrum is aggregated with a LE supplementary cell operating in a time sharing mode for uplink (UL) and downlink (DL) operations. The LE supplementary cell may be an FDD supplementary cell dynamically configurable between an UL only mode, a DL only mode, and a shared mode, to match requested UL and DL traffic ratios. The LE supplementary cell may be a time division duplex (TDD) supplementary cell. The TDD supplementary cell may be dynamically configurable between multiple TDD configurations. A coexistence capability for coordinating operations between the LE supplementary cell with other systems operating in the same channel is provided. Coexistence gaps are provided to measure primary/secondary user usage and permit other systems operating in the LE supplementary cell channel to access the channel.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: January 30, 2018
    Assignee: InterDigital Patent Holdings, Inc.
    Inventors: Jean-Louis Gauvreau, Martino M. Freda, Zinan Lin, Joseph M. Murray, Chunxuan Ye, Erdem Bala, Mihaela C. Beluri, Douglas R. Castor, Amith V. Chincholi, Angelo A. Cuffaro, Yuying Dai, Alpaslan Demir, Joseph Gredone, Rui Yang, Liangping Ma, Rocco Di Girolamo, Debashish Purkayastha, Athmane Touag
  • Patent number: 9756037
    Abstract: A certification provenance tree (CPT) structure may provide information concerning a layered certification of a device that comprises a hierarchy of components. The CPT structure may include a hierarchy of secure certification provenance document (SCPD) structures. Each SCPD structure in the hierarchy may represent a given component at a given level of the hierarchy of components of the device. Each SCPD structure may include a field that stores a certification proof indicating that security properties of the given component have been certified by a certification authority. An SCPD structure may further include accreditation information fields that store a pointer to an SCPD structure of a component at a next layer of the hierarchy of components of the device. The pointer may provide an indication of assurance that the component at that next layer will perform securely within this component at said given layer.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: September 5, 2017
    Assignee: InterDigital Patent Holdings, Inc.
    Inventors: Dolores F. Howry, Yogendra C. Shah, Alec Brusilovsky, Joseph Gredone
  • Publication number: 20160337090
    Abstract: A method and apparatus for operating supplementary cells in licensed exempt (LE) spectrum. An aggregating cell operating in a frequency division duplex (FDD) licensed spectrum is aggregated with a LE supplementary cell operating in a time sharing mode for uplink (UL) and downlink (DL) operations. The LE supplementary cell may be an FDD supplementary cell dynamically configurable between an UL only mode, a DL only mode, and a shared mode, to match requested UL and DL traffic ratios. The LE supplementary cell may be a time division duplex (TDD) supplementary cell. The TDD supplementary cell may be dynamically configurable between multiple TDD configurations. A coexistence capability for coordinating operations between the LE supplementary cell with other systems operating in the same channel is provided. Coexistence gaps are provided to measure primary/secondary user usage and permit other systems operating in the LE supplementary cell channel to access the channel.
    Type: Application
    Filed: July 25, 2016
    Publication date: November 17, 2016
    Applicant: InterDigital Patent Holdings, Inc.
    Inventors: Jean-Louis Gauvreau, Martino M. Freda, Zinan Lin, Joseph M. Murray, Chunxuan Ye, Erdem Bala, Mihaela C. Beluri, Douglas R. Castor, Amith V. Chincholi, Angelo A. Cuffaro, Yuying Dai, Alpaslan Demir, Joseph Gredone, Rui Yang, Liangping Ma, Rocco Di Girolamo, Debashish Purkayastha, Athmane Touag
  • Publication number: 20140129815
    Abstract: A device may include a trusted component. The trusted component may be verified by a trusted third party and may have a certificate of verification stored therein based on the verification by the trusted third party. The trusted component may include a root of trust that may provide secure code and data storage and secure application execution. The root of trust may also be configured to verify an integrity of the trusted component via a secure boot and to prevent access to the certain information in the device if the integrity of the trusted component may not be verified.
    Type: Application
    Filed: April 15, 2010
    Publication date: May 8, 2014
    Applicant: InterDigital Patent Holdings, Inc.
    Inventors: Yogendra C. Shah, Inhyok Cha, Andreas Schmidt, Andreas Leicher, Joseph Gredone, Samian J. Kaur
  • Patent number: 8701205
    Abstract: A device may include a trusted component. The trusted component may be verified by a trusted third party and may have a certificate of verification stored therein based on the verification by the trusted third party. The trusted component may include a root of trust that may provide secure code and data storage and secure application execution. The root of trust may also be configured to verify an integrity of the trusted component via a secure boot and to prevent access to the certain information in the device if the integrity of the trusted component may not be verified.
    Type: Grant
    Filed: April 15, 2010
    Date of Patent: April 15, 2014
    Assignee: InterDigital Patent Holdings, Inc.
    Inventors: Yogendra C. Shah, Inhyok Cha, Andreas Schmidt, Andreas Leicher, Joseph Gredone, Samian Kaur
  • Publication number: 20140082352
    Abstract: A certification provenance tree (CPT) structure may provide information concerning a layered certification of a device that comprises a hierarchy of components. The CPT structure may include a hierarchy of secure certification provenance document (SCPD) structures. Each SCPD structure in the hierarchy may represent a given component at a given level of the hierarchy of components of the device. Each SCPD structure may include a field that stores a certification proof indicating that security properties of the given component have been certified by a certification authority. An SCPD structure may further include accreditation information fields that store a pointer to an SCPD structure of a component at a next layer of the hierarchy of components of the device. The pointer may provide an indication of assurance that the component at that next layer will perform securely within this component at said given layer.
    Type: Application
    Filed: September 19, 2013
    Publication date: March 20, 2014
    Inventors: Dolores F. Howry, Yogendra C. Shah, Alec Brusilovsky, Joseph Gredone
  • Publication number: 20110099361
    Abstract: A device may include a trusted component. The trusted component may be verified by a trusted third party and may have a certificate of verification stored therein based on the verification by the trusted third party. The trusted component may include a root of trust that may provide secure code and data storage and secure application execution. The root of trust may also be configured to verify an integrity of the trusted component via a secure boot and to prevent access to the certain information in the device if the integrity of the trusted component may not be verified.
    Type: Application
    Filed: April 15, 2010
    Publication date: April 28, 2011
    Applicant: InterDigital Patent Holdings, Inc.
    Inventors: Yogendra C. Shah, Inhyok Cha, Andreas Schmidt, Andreas Leicher, Joseph Gredone
  • Patent number: 7752482
    Abstract: A hybrid serial/parallel bus interface has a data block demultiplexing device. The data block demultiplexing device has an input configured to receive a data block and demultiplexes the data block into a plurality of nibbles. For each nibble, a parallel to serial converter converts the nibble into serial data. A line transfers each nibble's serial data. A serial to parallel converter converts each nibble's serial data to recover that nibble. A data block reconstruction device combines the recovered nibbles into the data block. The data block is employed by a gain controller. Each nibble has at least two start bits whose states collectively represent both a function and/or destination.
    Type: Grant
    Filed: July 3, 2008
    Date of Patent: July 6, 2010
    Assignee: InterDigital Technology Corporation
    Inventors: Joseph Gredone, Alfred Stufflet, Timothy A. Axness
  • Patent number: 7475273
    Abstract: A hybrid serial/parallel bus interface has a data block demultiplexing device. The data block demultiplexing device has an input configured to receive a data block and demultiplexes the data block into a plurality of nibbles. For each nibble, a parallel to serial converter converts the nibble into serial data. A line transfers each nibble's serial data. A serial to parallel converter converts each nibble's serial data to recover that nibble. A data block reconstruction device combines the recovered nibbles into the data block. The data block is employed by a gain controller.
    Type: Grant
    Filed: January 3, 2007
    Date of Patent: January 6, 2009
    Assignee: InterDigital Technology Corporation
    Inventors: Joseph Gredone, Alfred Stufflet, Timothy A. Axness
  • Publication number: 20080268800
    Abstract: A hybrid serial/parallel bus interface has a data block demultiplexing device. The data block demultiplexing device has an input configured to receive a data block and demultiplexes the data block into a plurality of nibbles. For each nibble, a parallel to serial converter converts the nibble into serial data. A line transfers each nibble's serial data. A serial to parallel converter converts each nibble's serial data to recover that nibble. A data block reconstruction device combines the recovered nibbles into the data block. The data block is employed by a gain controller. Each nibble has at least two start bits whose states collectively represent both a function and/or destination.
    Type: Application
    Filed: July 3, 2008
    Publication date: October 30, 2008
    Applicant: INTERDIGITAL TECHNOLOGY CORPORATION
    Inventors: Joseph Gredone, Alfred Stufflet, Timothy A. Axness
  • Patent number: 7240233
    Abstract: A hybrid serial/parallel bus interface has a data block demultiplexing device. The data block demultiplexing device has an input configured to receive a data block and demultiplexes the data block into a plurality of nibbles. For each nibble, a parallel to serial converter converts the nibble into serial data. A line transfers each nibble's serial data. A serial to parallel converter converts each nibble's serial data to recover that nibble. A data block reconstruction device combines the recovered nibbles into the data block. The data block is employed by a gain controller.
    Type: Grant
    Filed: June 13, 2005
    Date of Patent: July 3, 2007
    Assignee: Interdigital Technology Corporation
    Inventors: Joseph Gredone, Alfred Stufflet, Timothy A. Axness
  • Publication number: 20070113117
    Abstract: A hybrid serial/parallel bus interface has a data block demultiplexing device. The data block demultiplexing device has an input configured to receive a data block and demultiplexes the data block into a plurality of nibbles. For each nibble, a parallel to serial converter converts the nibble into serial data. A line transfers each nibble's serial data. A serial to parallel converter converts each nibble's serial data to recover that nibble. A data block reconstruction device combines the recovered nibbles into the data block. The data block is employed by a gain controller.
    Type: Application
    Filed: January 3, 2007
    Publication date: May 17, 2007
    Applicant: InterDigital Technology Corporation
    Inventors: Joseph Gredone, Alfred Stufflet, Timothy Axness
  • Patent number: 7107479
    Abstract: A hybrid serial/parallel bus interface method and apparatus for a base station has a data block demultiplexing device. The data block demultiplexing device has an input configured to receive a data block and demultiplexes the data block into a plurality of nibbles. For each nibble, a parallel to serial converter converts the nibble into serial data. A line transfers each nibble's serial data. A serial to parallel converter converts each nibble's serial data to recover that nibble. A data block reconstruction device combines the recovered nibbles into the data block. The method/apparatus is adaptable for either bidirectional or unidirectional applications.
    Type: Grant
    Filed: December 2, 2004
    Date of Patent: September 12, 2006
    Assignee: InterDigital Technology Corporation
    Inventors: Joseph Gredone, Alfred W. Stufflet, Timothy A. Axness
  • Patent number: 7069464
    Abstract: A hybrid serial/parallel bus interface has a data block demultiplexing device. The data block demultiplexing device has an input configured to receive a data block and demultiplexes the data block into a plurality of nibbles. For each nibble, a parallel to serial converter converts the nibble into serial data. A line transfers each nibble's serial data. A serial to parallel converter converts each nibble's serial data to recover that nibble. A data block reconstruction device combines the recovered nibbles into the data block.
    Type: Grant
    Filed: November 21, 2001
    Date of Patent: June 27, 2006
    Assignee: Interdigital Technology Corporation
    Inventors: Joseph Gredone, Alfred Stufflet, Timothy A. Axness
  • Publication number: 20050250461
    Abstract: A hybrid serial/parallel bus interface has a data block demultiplexing device. The data block demultiplexing device has an input configured to receive a data block and demultiplexes the data block into a plurality of nibbles. For each nibble, a parallel to serial converter converts the nibble into serial data. A line transfers each nibble's serial data. A serial to parallel converter converts each nibble's serial data to recover that nibble. A data block reconstruction device combines the recovered nibbles into the data block. The data block is employed by a gain controller.
    Type: Application
    Filed: June 13, 2005
    Publication date: November 10, 2005
    Applicant: InterDigital Technology Corporation
    Inventors: Joseph Gredone, Alfred Stufflet, Timothy Axness
  • Publication number: 20050105370
    Abstract: A hybrid serial/parallel bus interface method and apparatus for a base station has a data block demultiplexing device. The data block demultiplexing device has an input configured to receive a data block and demultiplexes the data block into a plurality of nibbles. For each nibble, a parallel to serial converter converts the nibble into serial data. A line transfers each nibble's serial data. A serial to parallel converter converts each nibble's serial data to recover that nibble. A data block reconstruction device combines the recovered nibbles into the data block. The method/apparatus is adaptable for either bidirectional or unidirectional applications.
    Type: Application
    Filed: December 2, 2004
    Publication date: May 19, 2005
    Applicant: InterDigital Technology Corporation
    Inventors: Joseph Gredone, Alfred Stufflet, Timothy Axness
  • Patent number: 6848018
    Abstract: A hybrid serial/parallel bus interface method for a base station has a data block demultiplexing device. The data block demultiplexing device has an input configured to receive a data block and demultiplexes the data block into a plurality of nibbles. For each nibble, a parallel to serial converter converts the nibble into serial data. A line transfers each nibble's serial data. A serial to parallel converter converts each nibble's serial data to recover that nibble. A data block reconstruction device combines the recovered nibbles into the data block.
    Type: Grant
    Filed: February 22, 2002
    Date of Patent: January 25, 2005
    Assignee: InterDigital Technology Corporation
    Inventors: Joseph Gredone, Alfred Stufflet, Timothy A. Axness