Abstract: A method for reducing fetch time in a computer system provides a memory fetch cycle that is shorter than the memory store cycle. Each chip of the computer system has at least one dynamic random access memory array (DRAM) and a small high speed cache static random access memory (SRAM) on the chip. The system memory controller recognizes the fetch or store state of a memory request in generating a DRAM subrow-address timing signal (RAS) and a cache address timing signal (CAS) for enabling the accessing and addressing of bits in the SRAM and recovery in the DRAM. The RAS starts DRAM recovery for a fetch cycle at or near the start of fetching of data from the SRAMs on the chips, but controls RAS to not start DRAM recovery for a store cycle until SRAM data storing is done. The clocks on the chips contain circuits that control DRAM recovery while fetching during DRAM data from the SRAMs, but that prevent DRAM recovery from starting until data storing in the SRAMs is complete.