Abstract: A TDMA terminal is disclosed having a plurality of terrestrial interface ports, and a plurality of modems for modulating preamble and port data onto a carrier and demodulating the received data transmitted via a satellite from the carrier wherein the interface ports and modems are fully connected over a common bus arrangement. The TDMA terminal controller defines the sequence of transmission (TX) and reception (RX) of information through these multiple ports and modems. The control sequencing selectively activates the ports and modems to accommodate current traffic requirements. This is achieved by presenting clock timing signals and port address signals repetitively to the ports during each transmission frame to couple the ports to the bus for transmit and receive information during the allocated burst intervals. This sequencing system adds or deletes bursts, for selectively defining the ports and modems to be coupled to the bus.

Abstract: A microprogrammable TDMA terminal controller is of modular construction. Frame reference and burst synchronization timing are resolved to the symbol level by a split frame counter, and a control RAM is reprogrammable "on-the-fly" to permit easy changes in terminal traffic assignments. The terminal controller includes a microprogrammed RAM controller for performing real time burst and data path control functions, transmit and receive high-speed data path modules for interfacing with the modem and terrestrial interface ports and providing direct burst processing of the data, a microcomputer-based operation control and a high stability oscillator.

Abstract: A plurality of terrestrial interface modules (TIMs) are multiplexed and demultiplexed with common equipment through the use of mapping RAMs contained in each TIM. The common equipment provides identical addresses to each of the mapping RAMs in the TIMs. The mapping RAMs in each TIM determine whether incoming or outgoing data is to be written into or read from the associated TIM, and generate an address for the data so written into or read from the TIM. A mapping RAM is further provided in the common equipment to allow for burst-to-burst selection of data.

Abstract: A common memory is used for asynchronous interleaved read and write operations. TDMA data compression and expansion is performed without ping-pong memories and elastic buffering is also possible. A buffer reset method is used to automatically slip a fixed number of bits in response to excessive phase shift between the read and write clock.