Patents by Inventor Joseph H. Lyons

Joseph H. Lyons has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6984836
    Abstract: A system for monitoring wafer surface topography during a lithographic process is described that includes projection optics that illuminate a portion of the wafer surface. The system further includes at least one off-axis wafer surface gauge that monitors wafer surface height relative to the projection optics as well as at least one backplane gauge that monitors wafer position relative to a backplane. The system also includes a filter that translates time-domain measurements of off-axis wafer surface gauge and the backplane gauge into space-domain measurements. A coordinate transformer is included that transforms the space-domain measurements into a single coordinate system. A computational element that combines the space-domain measurements with a focus set-point to determine correction data is also included together with a delay line for storing the correction data until the wafer has moved a predetermined distance.
    Type: Grant
    Filed: May 12, 2003
    Date of Patent: January 10, 2006
    Assignee: ASML Holding N.V.
    Inventor: Joseph H. Lyons
  • Patent number: 6979833
    Abstract: A system for monitoring wafer surface topography during a lithographic process is described that includes means for capturing wafer position and surface data at a first time when a wafer is at a first location, means for generating correction data for a second wafer location prior to the wafer reaching the second wafer location, and means for storing the correction data in a spatial delay line. The means for capturing wafer position and surface data includes means for capturing backplane position data with a plurality of stalk gauges. The means for generating correction data includes means for converting the wafer position and surface data from a time-domain into a space domain. The system also includes means for moving the wafer based on the correction data when the wafer is at the second wafer location at a second time.
    Type: Grant
    Filed: July 14, 2004
    Date of Patent: December 27, 2005
    Assignee: ASML Holding N.V.
    Inventor: Joseph H. Lyons
  • Patent number: 6885429
    Abstract: A system and method are used to calibrate a focus portion of an exposure section of a lithography tool. A wafer is exposed so that a resulted or formed patterned image is tilted with respect to the wafer. The tilting can be imposed based on controlling a wafer stage to tilt the wafer or a reticle stage to tilt the reticle. The wafer is developed. Characteristics of the tilted patterned image are measured with a portion of the lithography tool to determine focus parameters of an exposure system. The portion can be an alignment system. The measuring step can measure band width and/or band location of the tilted patterned image. Sometimes, more than one patterned image is formed on the wafer, then the measuring step can measure distance between bands and shifting of the bands with respect to a central axis of the wafer. The focus parameters can be focus tilt errors and/or focus offset. The focus parameters are used to perform calibration.
    Type: Grant
    Filed: November 22, 2002
    Date of Patent: April 26, 2005
    Assignee: ASML Holding N.V.
    Inventors: Joseph H. Lyons, Joseph G. Whelan
  • Publication number: 20040001192
    Abstract: A system and method are used to calibrate a focus portion of an exposure section of a lithography tool. A wafer is exposed so that a resulted or formed patterned image is tilted with respect to the wafer. The tilting can be imposed based on controlling a wafer stage to tilt the wafer or a reticle stage to tilt the reticle. The wafer is developed. Characteristics of the tilted patterned image are measured with a portion of the lithography tool to determine focus parameters of an exposure system. The portion can be an alignment system. The measuring step can measure band width and/or band location of the tilted patterned image. Sometimes, more than one patterned image is formed on the wafer, then the measuring step can measure distance between bands and shifting of the bands with respect to a central axis of the wafer. The focus parameters can be focus tilt errors and/or focus offset. The focus parameters are used to perform calibration.
    Type: Application
    Filed: November 22, 2002
    Publication date: January 1, 2004
    Inventors: Joseph H. Lyons, Joseph G. Whelan
  • Publication number: 20030201405
    Abstract: A system for monitoring wafer surface topography during a lithographic process is described that includes projection optics that illuminate a portion of the wafer surface. The system further includes at least one off-axis wafer surface gauge that monitors wafer surface height relative to the projection optics as well as at least one backplane gauge that monitors wafer position relative to a backplane. The system also includes a filter that translates time-domain measurements of off-axis wafer surface gauge and the backplane gauge into space-domain measurements. A coordinate transformer is included that transforms the space-domain measurements into a single coordinate system. A computational element that combines the space-domain measurements with a focus set-point to determine correction data is also included together with a delay line for storing the correction data until the wafer has moved a predetermined distance.
    Type: Application
    Filed: May 12, 2003
    Publication date: October 30, 2003
    Inventor: Joseph H. Lyons
  • Patent number: 6633050
    Abstract: A virtual gauging system for use in a lithographic process is described that includes means for gauging a region at a surface of a wafer when the region is located away from an axis of illumination producing wafer surface data, while other portions of the wafer are being illuminated. The system also includes means for converting the wafer surface data into wafer correction data and means for adjusting a separation distance between an exposure lens and the region at the surface of the wafer based on the correction data when the region is located at the axis of illumination. The means for gauging includes at least two wafer surface gauges located on opposite sides of an illumination slot.
    Type: Grant
    Filed: August 15, 2000
    Date of Patent: October 14, 2003
    Assignee: ASML Holding NV.
    Inventor: Joseph H. Lyons