Abstract: Software Digital Front End (SoftDFE) signal processing techniques are provided. One or more digital front end (DFE) functions are performed on a signal in software by executing one or more specialized instructions on a processor to perform the one or more digital front end (DFE) functions on the signal, wherein the processor has an instruction set comprised of one or more of linear and non-linear instructions. A block of samples comprised of a plurality of data samples is optionally formed and the digital front end (DFE) functions are performed on the block of samples. The specialized instructions can include a vector convolution function, a complex exponential function, an xk function, a vector compare instruction, a vector max( ) instruction, a vector multiplication instruction, a vector addition instruction, a vector sqrt( ) instruction, a vector 1/x instruction, and a user-defined non-linear instruction.

Abstract: Software implementations are provided for performing IQ imbalance correction and/or RF equalization. An input signal, x, is processed in software by executing a vector convolution instruction to apply the input signal, x, to a first complex FIR filter that performs one or more of RF equalization and IQ imbalance correction; and executing a vector convolution instruction to apply a conjugate x* of the input signal, x, to a second complex FIR filter that performs the one or more of RF equalization and IQ imbalance correction, wherein the second complex FIR filter is in parallel with the first complex FIR filter. The first and second complex FIR filters have complex coefficients and the input signal comprises a complex signal.

Abstract: A digital processor is provided having an instruction set with a complex exponential function. The digital processor evaluates a complex exponential function for an input value, x, by obtaining a complex exponential software instruction having the input value, x, as an input; and in response to the complex exponential software instruction: invoking at least one complex exponential functional unit that implements complex exponential software instructions to apply the complex exponential function to the input value, x; and generating an output corresponding to the complex exponential of the input value, x. A complex exponential function for an input value, x, can be evaluated by wrapping the input value to maintain a given range; computing a coarse approximation angle using a look-up table; scaling the coarse approximation angle to obtain an angle from 0 to ?; and computing a fine corrective value using a polynomial approximation.

Abstract: Block-based crest factor reduction (CFR) techniques are provided. An exemplary block-based crest factor reduction method comprises obtaining a block of data samples comprised of a plurality of samples; applying the block of data to a crest factor reduction block; and providing a processed block of data from the crest factor reduction block. The block-based crest factor reduction method can optionally be iteratively performed a plurality of times for the block of data. The block of data samples can comprise an expanded block having at least one cursor block. For example, at least two pre-cursor blocks and one post-cursor block can be employed. The peaks can be cancelled, for example, only in the block of data samples and in a first of the pre-cursor blocks.

Abstract: A vector processor is provided having an instruction set with a vector convolution function. The disclosed vector processor performs a convolution function between an input signal and a filter impulse response by obtaining a vector comprised of at least N1+N2-1 input samples; obtaining N2 time shifted versions of the vector (including a zero shifted version), wherein each time shifted version comprises Ni samples; and performing a weighted sum of the time shifted versions of the vector by a vector of Ni coefficients; and producing an output vector comprising one output value for each of the weighted sums. The vector processor performs the method, for example, in response to one or more vector convolution software instructions having a vector input. The vector can comprise a plurality of real or complex input samples and the filter impulse response can be expressed using a plurality of coefficients that are real or complex.

Abstract: Software Digital Front End (SoftDFE) signal processing techniques are provided. One or more digital front end (DFE) functions are performed on a signal in software by executing one or more specialized instructions on a processor to perform the one or more digital front end (DFE) functions on the signal, wherein the processor has an instruction set comprised of one or more of linear and non-linear instructions. A block of samples comprised of a plurality of data samples is optionally formed and the digital front end (DFE) functions are performed on the block of samples. The specialized instructions can include a vector convolution function, a complex exponential function, an xk function, a vector compare instruction, a vector max( ) instruction, a vector multiplication instruction, a vector addition instruction, a vector sqrt( ) instruction, a vector 1/x instruction, and a user-defined non-linear instruction.

Abstract: Block-based crest factor reduction (CFR) techniques are provided. An exemplary block-based crest factor reduction method comprises obtaining a block of data samples comprised of a plurality of samples; applying the block of data to a crest factor reduction block; and providing a processed block of data from the crest factor reduction block. The block-based crest factor reduction method can optionally be iteratively performed a plurality of times for the block of data. The block of data samples can comprise an expanded block having at least one cursor block. For example, at least two pre-cursor blocks and one post-cursor block can be employed. The peaks can be cancelled, for example, only in the block of data samples and in a first of the pre-cursor blocks.

Abstract: A digital processor is provided having an instruction set with a complex exponential function. The digital processor evaluates a complex exponential function for an input value, x, by obtaining a complex exponential software instruction having the input value, x, as an input; and in response to the complex exponential software instruction: invoking at least one complex exponential functional unit that implements complex exponential software instructions to apply the complex exponential function to the input value, x; and generating an output corresponding to the complex exponential of the input value, x. A complex exponential function for an input value, x, can be evaluated by wrapping the input value to maintain a given range; computing a coarse approximation angle using a look-up table; scaling the coarse approximation angle to obtain an angle from 0 to ?; and computing a fine corrective value using a polynomial approximation.

Abstract: Methods and apparatus are provided for direct synthesis of RF signals using a delta-sigma modulator. An RF signal is synthesized from an input signal by quantizing the input signal using a quantizer, such as a one bit quantizer; determining a quantization error associated with the quantizer; generating an error prediction value using an error predictive filter, wherein the error predictive filter comprises one or more filter zeroes on a unit circle for one or more desired frequencies of f1, f2, . . . fn and one or more filter poles having a magnitude inside the unit circle and a frequency substantially equal to the one or more desired frequencies of f1, f2, . . . fn; and subtracting the error prediction value from the input signal. The filter poles have a magnitude that reduces a boost provided out-of-band.

Abstract: A search sphere-based linear block decoder is provided. A received vector, v, is decoded by computing a syndrome vector, S, corresponding to the received vector, v; (S=vH); obtaining a set of all possible error vectors, e, corresponding to the computed syndrome vector, S, wherein the set of all possible error vectors, e, is obtained from a pre-computed error table and has a specified maximum number of bit errors; calculating a set of all possible received vectors, x, based on the received vector, v, and the set of all possible error vectors, e; determining a k-bit code-vector x that is closest to the received vector, v; and determining an n-bit data-vector, d, associated with the k-bit code-vector x. The pre-computed error table can be generated by multiplying all possible error vectors by a Syndrome Matrix, to obtain all possible syndrome vectors associated with all possible error vectors.

Abstract: A search sphere-based linear block decoder is provided. A received vector, v, is decoded by computing a syndrome vector, S, corresponding to the received vector, v; (S=vH); obtaining a set of all possible error vectors, e, corresponding to the computed syndrome vector, S, wherein the set of all possible error vectors, e, is obtained from a pre-computed error table and has a specified maximum number of bit errors; calculating a set of all possible received vectors, x, based on the received vector, v, and the set of all possible error vectors, e; determining a k-bit code-vector x that is closest to the received vector, v; and determining an n-bit data-vector, d, associated with the k-bit code-vector x. The pre-computed error table can be generated by multiplying all possible error vectors by a Syndrome Matrix, to obtain all possible syndrome vectors associated with all possible error vectors.

Abstract: Methods and apparatus are provided for direct synthesis of RF signals using a delta-sigma modulator. An RF signal is synthesized from an input signal by quantizing the input signal using a quantizer, such as a one bit quantizer; determining a quantization error associated with the quantizer; generating an error prediction value using an error predictive filter, wherein the error predictive filter comprises one or more filter zeroes on a unit circle for one or more desired frequencies of f1, f2, . . . fn and one or more filter poles having a magnitude inside the unit circle and a frequency substantially equal to the one or more desired frequencies of f1, f2, . . . fn; and subtracting the error prediction value from the input signal. The filter poles have a magnitude that reduces a boost provided out-of-band.

Abstract: Methods and apparatus are provided for whitening quantization noise in a delta-sigma modulator using a dither signal. An input signal is quantized using a predictive delta-sigma modulator by quantizing the input signal using a quantizer; adding a dither signal at a first location of the predictive delta-sigma modulator; determining a quantization error associated with the quantizer; removing the dither signal at a second location of the predictive delta-sigma modulator (for example, by subtracting a substantially similar version of the dither signal at the second location); generating an error prediction value using an error predictive filter; and subtracting the error prediction value from the input signal. The dither signal may be a white noise signal and may optionally be generated using a pseudo-random number generator.

Abstract: Methods and apparatus are provided for look-ahead block processing in predictive delta-sigma modulators. An input signal is quantized using a predictive delta-sigma modulator by generating error prediction values for a current block of input values based on a linear combination of error prediction values from one or more previous blocks, input values of one or more previous blocks, quantized values of one or more previous blocks and the current block of input values; computing speculative error prediction values for at least one input value in the current block, wherein the speculative error prediction values are computed for a plurality of possible quantizer output values; selecting one of the speculative error prediction values based on a quantized value from the current block; and subtracting the error prediction values for the current block from the corresponding current block of input values.

Abstract: Methods and apparatus are provided for decorrelating quantization noise in a delta-sigma modulator. An input signal is quantized using a predictive delta-sigma modulator, by quantizing the input signal using a quantizer; determining a quantization error associated with the quantizer by subtracting an input to the quantizer from an output of the quantizer; measuring a correlation coefficient between the quantization error and an input to the quantizer; reducing the measured correlation by subtracting a multiple of the input to the quantizer from the quantization error, wherein the multiple is based on the correlation coefficient; generating an error prediction value using an error predictive filter; and subtracting the error prediction value from the input signal.

Abstract: Methods and apparatus are provided for decorrelating quantization noise in a delta-sigma modulator. An input signal is quantized using a predictive delta-sigma modulator, by quantizing the input signal using a quantizer; determining a quantization error associated with the quantizer by subtracting an input to the quantizer from an output of the quantizer; measuring a correlation coefficient between the quantization error and an input to the quantizer; reducing the measured correlation by subtracting a multiple of the input to the quantizer from the quantization error, wherein the multiple is based on the correlation coefficient; generating an error prediction value using an error predictive filter; and subtracting the error prediction value from the input signal.

Abstract: Methods and apparatus are provided for whitening quantization noise in a delta-sigma modulator using a dither signal. An input signal is quantized using a predictive delta-sigma modulator by quantizing the input signal using a quantizer; adding a dither signal at a first location of the predictive delta-sigma modulator; determining a quantization error associated with the quantizer; removing the dither signal at a second location of the predictive delta-sigma modulator (for example, by subtracting a substantially similar version of the dither signal at the second location); generating an error prediction value using an error predictive filter; and subtracting the error prediction value from the input signal. The dither signal may be a white noise signal and may optionally be generated using a pseudo-random number generator.

Abstract: Methods and apparatus are provided for look-ahead block processing in predictive delta-sigma modulators. An input signal is quantized using a predictive delta-sigma modulator by generating error prediction values for a current block of input values based on a linear combination of error prediction values from one or more previous blocks, input values of one or more previous blocks, quantized values of one or more previous blocks and the current block of input values; computing speculative error prediction values for at least one input value in the current block, wherein the speculative error prediction values are computed for a plurality of possible quantizer output values; selecting one of the speculative error prediction values based on a quantized value from the current block; and subtracting the error prediction values for the current block from the corresponding current block of input values.

Abstract: Efficient decoding of an hierarchical, variable length, encoded data sequence containing embedded uncoded data into a sequence of fixed length instructions for subsequent processing by a digital video processor or the like is realized in an apparatus including a decoder having a plurality of variable length code decoding elements and a control structure embedded within each decoding element for transferring the decoding operation to an appropriate one of the decoding elements in response to a prior output from the decoder element. As the encoded data sequence is processed by the apparatus, a predetermined length of the sequence is stored in a register. The control structure further responds to the encoded data sequence to initiate selection of either the predetermined length of the sequence stored in the register or a portion of the decoder output as the fixed length instruction to be output by the apparatus.