Abstract: A storage cell employs two conventional N-channel MOS transistors and an inverted N-channel field-effect transistor along with an implanted polysilicon resistor and a resistor implanted under field oxide which functions as a junction field effect transistor. All of the transistors and a storage node as well as a voltage supply line are in one continuous moat region for a dense layout with a minimum of contacts. One MOS transistor is the access device connected between a bit line and the storage node with its gate connected to an address line. The other MOS transistor connects the storage node to the supply line and has its gate controlled by a second node which is connected to the supply line by a polycrystalline silicon strip which is the source-to-drain path of the inverted field-effect transistor; the gate of this device is a part of the moat which forms the storage node.

Abstract: An MOS/LSI semiconductor chip for providing the functions of an electronic calculator or digital processor includes a RAM for data storage, a ROM for program instruction storage, an arithmetic unit for performing operations on data, and control circuitry for defining the functions of the machine in response to instructions from the ROM as well as conditions in the machine and inputs from external. The operation is digit oriented in that in a basic machine cycle one digit of the RAM is accessed. Also, in a machine cycle the ROM is addressed to provide an instruction word, and the word is decoded and executed. A unique five phase clocking arrangement is used which permits the complex operations to be implemented within a machine cycle.

Abstract: An ion-implanted lightly-doped polycrystalline silicon strip in an N-channel silicon gate integrated circuit device functions as a resistor element which exhibits transistor action. The impedance of the resistor element changes in response to the voltage on an underlying polycrystalline silicon area which is insulated from the resistor element by a thin silicon oxide layer. This resistor element is used as a load in a static RAM cell array and lowers the power dissipation of the array; the resistance is high for stored zeros and low for stored logic ones.

Abstract: A double-level polycrystalline silicon structure for an N-channel MOS integrated circuit is disclosed including a metal interconnect level. Contact between the metal interconnect level and N+ diffused moat areas is made through discrete second-level polysilicon areas which reduce the step from metal level to moat level, thus increasing yields. Also, connections from the metal level to the first level polysilicon are made using a discrete area of second level polysilicon to minimize the step.

Abstract: Integrated circuit resistor elements ideally suited for load devices in static MOS RAM cells are made in second-level polycrystalline silicon by an ion implant step compatible with a self-aligned N-channel silicon-gate process. The cell size is reduced as the resistors can overly the first-level poly or MOS transistors. The second-level poly does not form transistor gates, so it is less critical, and an efficient layout provides a very small cell area.

Abstract: A storage cell employs two conventional N-channel MOS transistors and an inverted N-channel field-effect transistor along with an implanted polysilicon resistor and a resistor implanted under field oxide which functions as a junction field effect transistor. All of the transistors and a storage node as well as a voltage supply line are in one continuous moat region for a dense layout with a minimum of contacts. One MOS transistor is the access device connected between a bit line and the storage node with its gate connected to an address line. The other MOS transistor connects the storage node to the supply line and has its gate controlled by a second node which is connected to the supply line by a polycrystalline silicon strip which is the source-to-drain path of the inverted field-effect transistor; the gate of this device is a part of the moat which forms the storage node.

Abstract: An MOS/LSI semiconductor chip for providing the functions of an electronic calculator or digital processor includes a RAM for data storage, a ROM for program instruction storage, an arithmetic unit for performing operations on data, and control circuitry for defining the functions of the machine in response to instructions from the ROM as well as conditions in the machine and inputs from external. The operation is digit oriented in that in a basic machine cycle one digit of the RAM is accessed. Also, in a machine cycle the ROM is addressed to provide an instruction word, and the word is decoded and executed. A unique five phase clocking arrangement is used which permits the complex operations to be implemented within a machine cycle.

Abstract: An MOS/LSI semiconductor chip for providing the functions of an electronic calculator or digital processor includes a data memory, an arithmetic unit for executing operations on data, and a control arrangement for defining the functioning of the machine including a ROM for storing a large number of instruction words, and control decoders for receiving instruction words from the ROM and producing various commands for the control arrangement. Separate X and Y address registers are provided for selecting the location in the ROM for the next instruction. Input and output terminals are provided, as for keyboard input, and display output. A test mode of operation is provided for quality control upon completion of manufacture of the chip.

Abstract: An MOS/LSI semiconductor chip for providing the functions of an electronic calculator or digital processor includes a RAM for data storage, a ROM for program instruction storage, an arithmetic unit for performing operations on data, and control circuitry for defining the functions of the machine in response to instructions from the ROM as well as conditions in the machine and inputs from external. The operation is digit oriented in that in a machine cycle one digit of the RAM is accessed, and also the ROM is addressed to provide an instruction word which is decoded and executed. The data input to the system is by four parallel lines which may be connected to a scanned keyswitch matrix or to BCD or binary data sources. Within the chip, the data inputs may be coupled to the input of the arithmetic unit, or to the data memory directly.

Abstract: An MOS/LSI semiconductor chip for providing the functions of an electronic calculator or digital processor includes a data storage RAM, a ROM for program instruction storage, an arithmetic unit for performing operations on data, and control circuitry for defining the functions of the machine in response to instructions from the ROM as well as conditions in the machine and inputs from external. Input and output terminals are provided, as for keyboard input and display output. The operation is digit oriented in that an instruction accesses one digit of the RAM. One set of output terminals may be used for sequentially scanning the display digits and the keyboard matrix, while another set of output terminals may provide segment outputs to the display. The two sets of output terminals are separately controllable. The terminals going to the display digits can be actuated in any order, not necessarily associated with any particular digit being applied to the segment outputs.

Abstract: An MOS/LSI semiconductor chip for providing the functions of an electronic calculator or digital processor includes a data storage RAM, a ROM for program instruction storage, an arithmetic unit for performing operations on data, and control circuitry for defining the functions of the machine in response to instructions from the ROM as well as conditions in the machine and inputs from external. Input and output terminals are provided, as for keyboard input and display output. The operation is digit oriented in that an instruction accesses one digit of the RAM. One set of output terminals may be used for sequentially scanning the display digits and keyboard matrix; several of these may be actuated in any order or code combination, so the same terminals may be used to address an auxiliary RAM or drive a printer. Another set of output terminals may provide the segment outputs to the display. The two sets of output terminals are separately controllable.

Abstract: An MOS/LSI semiconductor chip for providing the functions of an electronic calculator or digital processor includes an data storage RAM, a ROM for program instruction storage, an arithmetic unit for performing operations on data, and control circuitry for defining the functions of the machine in response to instructions from the ROM as well as conditions in the machine and inputs from external. Input and output terminals are provided, as for keyboard input and display output. The operation is digit oriented in that an instruction accesses one digit of the RAM. A special circuit is used which combines several data and control functions including transfer of constants used in calculations from the ROM to the data registers, transfer of keyboard or other data from parallel input lines to an accumulator register or data memory, or to the adder for test or compare, and selection of one of four bits of a digit in data memory for set or reset.

Abstract: An MOS/LSI semiconductor chip for providing the functions of an electronic calculator or digital processor includes a RAM for data storage, a ROM for program instruction storage, an arithmetic unit for performing operations on data, and control circuitry for defining the functions of the machine in response to instructions from the ROM as well as conditions in the machine and inputs from external. The operation is digit oriented in that in a basic machine a cycle one digit of the RAM is accessed. In the machine cycle the ROM is also addressed to provide an instruction word, and the word is decoded and executed. The output of the arithmetic unit may be coupled to either a one digit accumulator or a one digit RAM address register.

Abstract: A memory cell comprising field effect transistors for use in a random access memory array. The cell is of the dynamic type wherein data is stored on capacitive elements, and is self-refreshing; no circuitry external to the array is needed for refresh, other than clock sources. Five MOS field effect transistors are employed, with two non-overlapping clocks, a data buss for each row of the array and one address line for each column. The transistors and associated capacitors are arranged to reinforce a stored "1" or "0".