Abstract: A test device for an integrated circuit utilizes current mode test signal shaping to evaluate circuit performance within at least one selected voltage swing. An interface circuit has an output line that is coupled to the integrated circuit under test. An upper voltage level (V.sub.OH) is established by a connection of the output line to a voltage source. The connection to the source includes a resistor. Parallel switchable current paths to a voltage level significantly less than V.sub.OH are also formed from the output line. In the preferred embodiment, the current paths are MOS transistors to electrical ground. The transistors in an "on" state act as current sinks that create a greater voltage drop across the resistor. Consequently, there is a correspondence between the number of transistors that are switched by input of a test signal and the difference between V.sub.OH and V.sub.OL. In the preferred embodiment, the interface circuit is used in the testing of a memory circuit, such as DRAM.

Abstract: A shared memory multiprocessor computer system in which one or more processor modules and/or input/output modules have cache memories. The main memory controller for each main memory of the system maintains a duplicate cache tag array containing current information on the status of data lines from the main memory that are stored in the cache memories. Thus, coherency checks can be performed directly by the main memory controller. This eliminates the need for each processor having a cache memory to perform a separate coherency check and to communicate the results of its coherency checks to the main memory controller, and thereby reduces delays associated with processing coherent transactions.