Patents by Inventor Joseph Harker

Joseph Harker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170069914
    Abstract: Embodiments include a grid for a battery. The grid can include a grid network bordered by at least one frame element having a current collector lug. The grid network can include a plurality of spaced apart generally vertically extending and generally horizontally extending grid wire elements. Each grid wire element has opposed ends. Each opposed end can be joined to one of a plurality of nodes to define a plurality of open spaces. Selected ones of the grid wire elements being joined at one of their ends to the one or more frame elements, wherein the wire elements have a cross-section that comprises at least one concave surface. Other embodiments are also included herein.
    Type: Application
    Filed: August 26, 2016
    Publication date: March 9, 2017
    Inventors: Kenneth Willard Lancaster, Brian Joseph Harker
  • Publication number: 20160359170
    Abstract: Grid for battery having a plurality of spaced apart vertically extending and horizontally extending grid wire elements with each grid wire element having opposed ends joined to one of a plurality of nodes to define a plurality of open spaces and with selected ones of the grid wire elements being joined at one of their ends to the frame elements. Oppositely facing sides of the grid wire elements define first and second planes that are parallel to each other. Selected frame elements have an undulating cross section across the width thereof with an apex of the undulation on one side of the grid being tangential to or terminating at a third plane that is separate from and parallel to the first and second planes.
    Type: Application
    Filed: June 8, 2016
    Publication date: December 8, 2016
    Inventors: Brian Joseph Harker, Kenneth Willard Lancaster
  • Patent number: 8904926
    Abstract: A hay press configured to generally (i) receive hay bales; (ii) cut the twine holding the hay bales together; (iii) move, by weight, a pre-established amount of hay into a compression chamber; (iv) compress the pre-established amount of hay into a package of pre-established size; and (v) eject and wrap the compressed package of hay for shipping. The hay press includes a (i) loading table and destacker; (ii) twine slicer; (iii) loading compartment; (iv) loading hydraulic press and platen; (v) infeed forks; (vi) compression chamber; (vii) scale; (viii) compression chamber door; (ix) hydraulic compression ram and platen; (x) hydraulic ejection press and platen; and (xi) ejection chute. An optional conveyor system may operate in conjunction with the hay press to transport loose hay having fallen during operation of the hay press to a loose hay loading chamber.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: December 9, 2014
    Inventor: Joseph Harker
  • Patent number: 8751836
    Abstract: A control processor manages the power budget in a drive enclosure and is within the drive enclosure which monitors in real time a redundantly configured power supply unit, drives, interposers, and temperature sensors, and determines the power settings for each drive to avoid overload and overheating in the system. The control processor dynamically adjusts the mode of operation as needed during operation through the SAS interposer. A localized monitoring and control mechanism eliminates the need for extraneous coordination of information across various entities that access the storage. Data tunneling takes place directly between the compute nodes and target drives through the SAS expander and interposer, and does not need buffering the pending IO requests in the DRAM.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: June 10, 2014
    Assignee: DataDirect Networks, Inc.
    Inventors: Michael J. Piszczek, Manjari Mishra, William Joseph Harker, Andrew Pershall, David F. Fellinger
  • Patent number: 8719520
    Abstract: A system for data migration between high performance computing architectures and data storage disks includes an intermediate data migration handling system which has an intermediate data storage module coupled to the computer architecture to store data received, and a data controller module which includes data management software supporting the data transfer activity between the intermediate data storage module and the disk drives in an orderly manner independent of the random I/O activity of the computer architecture. RAID calculations are performed on the data prior to storage in the intermediate storage module, as well as when reading data from it for assuring data integrity, and carrying out reconstruction of corrupted data. The data transfer to the disk drives is actuated in sequence determined by the data management software based on minimization of seeking time, tier usage, predetermined time since the previous I/O cycle, or fullness of the intermediate data storage module.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: May 6, 2014
    Assignee: DataDirect Networks, Inc.
    Inventors: Michael J. Piszczek, Cedric T. Fernandes, Dave F. Fellinger, William Joseph Harker, John Gordon Manning, Lee Douglas McBryde, Pavan Kumar Uppu, Manjari Mishra, Thomas Edward Fugini, Shivkumar Pandit, John Albert de Leon
  • Patent number: 8181089
    Abstract: A method for auto-correction of errors in an array of solid-state storage devices having a plurality of storage channels dedicated to storing parity data to provide fault tolerance for a loss of at least two of the plurality of storage channels. A read operation from the storage channels transfers data to a plurality of channel memories. The data in the channel memories is checked to confirm the data is valid. Responsive to detection of invalid data, the data may be tested to identify the storage channel in error, including sequentially excluding data read form a different one of the plurality of channel memories from a parity check and determining the validity of data from remaining channel memories. If valid data is obtained, the storage channel from which the data was excluded is identified as the storage channel in error.
    Type: Grant
    Filed: August 8, 2011
    Date of Patent: May 15, 2012
    Assignee: DataDirect Networks, Inc.
    Inventors: Cedric T. Fernandes, John Gordon Manning, Michael J. Piszczek, Lee Douglas McBryde, William Joseph Harker
  • Patent number: 8020074
    Abstract: A method for auto-correction of errors in an array of disk storage devices having a plurality of disk storage devices dedicated to storing parity data to provide fault tolerance for a loss of at least two of the plurality of disk storage devices. A read operation from the storage channels transfers data to a plurality of disk channel memories. The data in the disk channel memories is checked to confirm the data is valid. Responsive to detection of invalid data, the data may be tested to identify the disk storage channel in error, including sequentially excluding data read from a different one of the plurality of disk channel memories from a parity check and determining the validity of data from remaining disk channel memories. If valid data is obtained, the disk storage channel from which the data was excluded is identified as the disk storage channel in error.
    Type: Grant
    Filed: August 24, 2007
    Date of Patent: September 13, 2011
    Assignee: Datadirect Networks, Inc.
    Inventors: Cedric T. Fernandes, John Gordon Manning, Michael J. Piszczek, Lee Douglas McBryde, William Joseph Harker
  • Publication number: 20090055585
    Abstract: A method for auto-correction of errors in an array of disk storage devices (210) having a plurality of disk storage devices (210I, 210J) dedicated to storing parity data to provide fault tolerance for a loss of at least two of the plurality of disk storage devices (210A-210J). A read operation from the storage channels (210A-210J) transfers data to a plurality of disk channel memories (220A-220J). The data in the disk channel memories (220A-220J) is checked to confirm the data is valid. Responsive to detection of invalid data, the data may be tested to identify the disk storage channel in error, including sequentially excluding data read from a different one of the plurality of disk channel memories (220A-220J) from a parity check and determining the validity of data from remaining disk channel memories. If valid data is obtained, the disk storage channel from which the data was excluded is identified as the disk storage channel in error.
    Type: Application
    Filed: August 24, 2007
    Publication date: February 26, 2009
    Applicant: DATADIRECT NETWORKS, INC.
    Inventors: CEDRIC T. FERNANDES, JOHN GORDON MANNING, MICHAEL J. PISZCZEK, LEE DOUGLAS McBRYDE, WILLIAM JOSEPH HARKER