Abstract: A method and apparatus for reducing leakage currents in a high voltage tolerant I/O buffer. An I/O buffer designed to tolerate high external voltages by blocking such voltages at a passgate in a p-output path that uses a device between a p-driver gate node and a p-gate node of the passgate to ensure that the p-transistor of the passgate is turned on when the p-driver is driving the pad high. A second device isolates the p-gate node of the passgate from the pad until a pad voltage reaches a predetermined level. Once the pad voltage reaches the predetermined level, the device drives the voltage at the p-gate node of the passgate to that of the pad. Maintaining the p-transistor of the passgate on while the p-driver is driving the pad high allows a rapid hard shut-off of the p-driver as the I/O buffer tri-states the pad.