Patents by Inventor Joseph Hawkins
Joseph Hawkins has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240156305Abstract: A quick release attachment assembly and system to releasably join a utensil to a stand mixer drivetrain. The system includes an assembly comprising one or more retaining balls to axially fix an attachment insert in the assembly and a plurality of cooperating walls to fix the attachment insert against rotational displacement.Type: ApplicationFiled: November 14, 2022Publication date: May 16, 2024Inventors: Matthew R. Hunter, Joseph Mazzella, Mason Hawkins
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Publication number: 20240149482Abstract: Systems and methods described herein are optimized for cutting sealing elements on packages using optical radiation. Packages can pass through a cutting device that applies the optical radiation to damage, vaporize, or cut the sealing element (e.g., tape) on the package. The systems and methods control several aspects of the cutting process to adjust throughput, improve efficiency, and reduce line stoppages. Systems can include an in-feed conveyor that orients packages and rejects packages that are out of specification, which can lead to issues such as jamming or damage to the equipment. Systems can include a variable-speed cut conveyor controlled by a computing system to dynamically adjust the speed of packages based upon historical cut quality, environmental measurement data, and height data related to a vertical dimension of the package.Type: ApplicationFiled: January 16, 2024Publication date: May 9, 2024Inventors: Bryan Hawkins, Joseph David Blackner, John Marshall Jones, Santos Cerda, JR., Geoffrey Michael Miller
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Patent number: 11936415Abstract: An air interface plane (AIP) of a radio frequency (RF) aperture includes: a circuit board having a first side and a second side opposite the first side; and a matrix of tapered elements arranged on the first side of the circuit board and secured to the circuit board, the matrix of tapered elements cooperating to at least one of receive or transmit an over-the-air RF signal. Suitably, each tapered element of the matrix has: a central hub extending along a longitudinal axis from a hub base which is proximate to the first side of the circuit board to an apex of the tapered element which is distal from the first side of the first circuit board; and a plurality of arms extending from the central hub at the apex of the tapered element, each of the plurality of arms including a first portion that projects the arm radially away from the longitudinal axis and a second portion that projects the arm longitudinally toward the first side of the circuit board.Type: GrantFiled: April 26, 2023Date of Patent: March 19, 2024Assignee: BATTELLE MEMORIAL INSTITUTEInventors: Raphael Joseph Welsh, Douglas A. Thornton, Mackenzie Jordan Hawkins, Micah John Meleski, Katherine M. Armitage, Daniel G. Loesch, Matthew E. Huntwork, David R. Chase, Erik W. Edwards, John Bartholomew, Thomas Lloyd Moffitt, Curt Hudberg
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Patent number: 11520626Abstract: A method and system for an enhanced weighted fair queuing technique for a resource are provided. A plurality of request streams is received at a requestor, each request stream including request messages from a process executing on the requestor. The request messages of each request stream are apportioned to an input queue associated with the request stream; each input queue has a weight. A virtual finish time is determined for each request message based, at least in part, on the weights of the input queues. A sequence of request messages is determined based, at least in part, on the virtual finish times of the request messages. The sequence of request messages is enqueued into an output queue. The sequence of request messages is sent to a resource, over a connection, which provides a service for each process.Type: GrantFiled: September 22, 2020Date of Patent: December 6, 2022Assignee: Arm LimitedInventors: Michael Andrew Campbell, Peter Owen Hawkins, David Joseph Hawkins
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Patent number: 11401510Abstract: Described herein is a method of generating in-vitro differentiated airway basal cells and compositions thereof. Also described herein is a method of treating a pulmonary disease comprising administering the in-vitro differentiated airway basal cells and compositions thereof. In another aspect, described herein is a disease model comprising patient-derived or genetically modified in-vitro differentiated airway basal cells and compositions thereof.Type: GrantFiled: February 19, 2021Date of Patent: August 2, 2022Assignees: TRUSTEES OF BOSTON UNIVERSITY, THE BOARD OF REGENTS OF THE UNIVERSITY OF TEXAS SYSTEMInventors: Finn Joseph Hawkins, Darrell N. Kotton, Shingo Suzuki, Brian R. Davis, Cristina BarillĂ
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Publication number: 20220091886Abstract: A method and system for an enhanced weighted fair queuing technique for a resource are provided. A plurality of request streams is received at a requestor, each request stream including request messages from a process executing on the requestor. The request messages of each request stream are apportioned to an input queue associated with the request stream; each input queue has a weight. A virtual finish time is determined for each request message based, at least in part, on the weights of the input queues. A sequence of request messages is determined based, at least in part, on the virtual finish times of the request messages. The sequence of request messages is enqueued into an output queue. The sequence of request messages is sent to a resource, over a connection, which provides a service for each process.Type: ApplicationFiled: September 22, 2020Publication date: March 24, 2022Applicant: Arm LimitedInventors: Michael Andrew Campbell, Peter Owen Hawkins, David Joseph Hawkins
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Patent number: 11181957Abstract: An improved apparatus and method for the protection of reset in systems with stringent safety goals that employ primary and shadow logic blocks with a lock-step checker to achieve functional safety, including those systems having very large fanout of primary and shadow reset signal trees. The disclosed apparatus and method support assertion of reset that is asynchronous to the system clock and deassertion of reset that is synchronous to the system clock. Shadow logic blocks have reset deasserted a fixed number of clock cycles after their respective primary logic blocks, thereby avoiding the requirement to synchronize the primary and shadow reset signal trees at each of their end points to ensure lock-step operation between the primary and shadow logic blocks.Type: GrantFiled: November 24, 2020Date of Patent: November 23, 2021Assignee: Arm LimitedInventors: Ramamoorthy Guru Prasadh, Tushar P Ringe, Kishore Kumar Jagadeesha, David Joseph Hawkins, Saira Samar Malik
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Publication number: 20210254016Abstract: Described herein is a method of generating in-vitro differentiated airway basal cells and compositions thereof. Also described herein is a method of treating a pulmonary disease comprising administering the in-vitro differentiated airway basal cells and compositions thereof. In another aspect, described herein is a disease model comprising patient-derived or genetically modified in-vitro differentiated airway basal cells and compositions thereof.Type: ApplicationFiled: February 19, 2021Publication date: August 19, 2021Applicants: TRUSTEES OF BOSTON UNIVERSITY, THE BOARD OF REGENTS OF THE UNIVERSITY OF TEXAS SYSTEMInventors: Finn Joseph HAWKINS, Darrell N. KOTTON, Shingo SUZUKI, Brian R. DAVIS, Cristina BARILLĂ€
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Patent number: 10761561Abstract: An apparatus and method for transmitting signals between two clock domains in which at least one of a phase and a frequency of clock signals in the two clock domains is misaligned. The apparatus includes a first primary interface and a first redundant interface in the first clock domain for receiving a primary signal and a first checking signal respectively, and a second primary interface and second redundant interface in the second clock domain for outputting the primary signal and a second redundant signal respectively. The primary signal and the checking signals are separated by a predetermined time delay and the second checking signal is generated in the second clock domain based on the primary signal. Checking circuitry is provided in the second clock domain to perform an error checking procedure based on the two checking signals and to provide the second checking signal to the second redundant interface.Type: GrantFiled: May 25, 2018Date of Patent: September 1, 2020Assignee: Arm LimitedInventors: Saira Samar Malik, David Joseph Hawkins, Andrew David Tune, Guanghui Geng, Julian Jose Hilgemberg Pontes
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Patent number: 10713187Abstract: A memory controller comprises memory access circuitry configured to initiate a data access of data stored in a memory in response to a data access hint message received from another node in data communication with the memory controller; to access data stored in the memory in response to a data access request received from another node in data communication with the memory controller and to provide the accessed data as a data access response to the data access request.Type: GrantFiled: July 25, 2019Date of Patent: July 14, 2020Assignee: ARM LimitedInventors: Michael Filippo, Jamshed Jalal, Klas Magnus Bruce, Paul Gilbert Meyer, David Joseph Hawkins, Phanindra Kumar Mannava, Joseph Michael Pusdesris
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Publication number: 20190361486Abstract: An apparatus and method for transmitting signals between two clock domains in which at least one of a phase and a frequency of clock signals in the two clock domains is misaligned. The apparatus includes a first primary interface and a first redundant interface in the first clock domain for receiving a primary signal and a first checking signal respectively, and a second primary interface and second redundant interface in the second clock domain for outputting the primary signal and a second redundant signal respectively. The primary signal and the checking signals are separated by a predetermined time delay and the second checking signal is generated in the second clock domain based on the primary signal. Checking circuitry is provided in the second clock domain to perform an error checking procedure based on the two checking signals and to provide the second checking signal to the second redundant interface.Type: ApplicationFiled: May 25, 2018Publication date: November 28, 2019Inventors: Saira Samar MALIK, David Joseph HAWKINS, Andrew David TUNE, Guanghui GENG, Julian Jose Hilgemberg PONTES
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Publication number: 20190347217Abstract: A memory controller comprises memory access circuitry configured to initiate a data access of data stored in a memory in response to a data access hint message received from another node in data communication with the memory controller; to access data stored in the memory in response to a data access request received from another node in data communication with the memory controller and to provide the accessed data as a data access response to the data access request.Type: ApplicationFiled: July 25, 2019Publication date: November 14, 2019Inventors: Michael FILIPPO, Jamshed JALAL, Klas Magnus BRUCE, Paul Gilbert MEYER, David Joseph HAWKINS, Phanindra Kumar MANNAVA, Joseph Michael PUSDESRIS
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Patent number: 10402425Abstract: Techniques provide for hardware accelerated data movement between main memory and an on-chip data movement system that comprises multiple core processors that operate on the tabular data. The tabular data is moved to or from the scratch pad memories of the core processors. While the data is in-flight, the data may be manipulated by data manipulation operations. The data movement system includes multiple data movement engines, each dedicated to moving and transforming tabular data from main memory data to a subset of the core processors. Each data movement engine is coupled to an internal memory that stores data (e.g. a bit vector) that dictates how data manipulation operations are performed on tabular data moved from a main memory to the memories of a core processor, or to and from other memories. The internal memory of each data movement engine is private to the data movement engine.Type: GrantFiled: July 24, 2018Date of Patent: September 3, 2019Assignee: Oracle International CorporationInventors: David A. Brown, Rishabh Jain, Michael Duller, Sam Idicula, Erik Schlanger, David Joseph Hawkins, Christopher Joseph Daniels
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Patent number: 10402349Abstract: A memory controller comprises memory access circuitry configured to initiate a data access of data stored in a memory in response to a data access hint message received from another node in data communication with the memory controller; to access data stored in the memory in response to a data access request received from another node in data communication with the memory controller and to provide the accessed data as a data access response to the data access request.Type: GrantFiled: February 8, 2017Date of Patent: September 3, 2019Assignee: ARM LimitedInventors: Michael Filippo, Jamshed Jalal, Klas Magnus Bruce, Paul Gilbert Meyer, David Joseph Hawkins, Phanindra Kumar Mannava, Joseph Michael Pusdesris
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Publication number: 20180329975Abstract: Techniques provide for hardware accelerated data movement between main memory and an on-chip data movement system that comprises multiple core processors that operate on the tabular data. The tabular data is moved to or from the scratch pad memories of the core processors. While the data is in-flight, the data may be manipulated by data manipulation operations. The data movement system includes multiple data movement engines, each dedicated to moving and transforming tabular data from main memory data to a subset of the core processors. Each data movement engine is coupled to an internal memory that stores data (e.g. a bit vector) that dictates how data manipulation operations are performed on tabular data moved from a main memory to the memories of a core processor, or to and from other memories. The internal memory of each data movement engine is private to the data movement engine.Type: ApplicationFiled: July 24, 2018Publication date: November 15, 2018Inventors: DAVID A. BROWN, RISHABH JAIN, MICHAEL DULLER, SAM IDICULA, ERIK SCHLANGER, DAVID JOSEPH HAWKINS, CHRISTOPHER JOSEPH DANIELS
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Patent number: 10061832Abstract: Techniques provide for hardware accelerated data movement between main memory and an on-chip data movement system that comprises multiple core processors that operate on the tabular data. The tabular data is moved to or from the scratch pad memories of the core processors. While the data is in-flight, the data may be manipulated by data manipulation operations. The data movement system includes multiple data movement engines, each dedicated to moving and transforming tabular data from main memory data to a subset of the core processors. Each data movement engine is coupled to an internal memory that stores data (e.g. a bit vector) that dictates how data manipulation operations are performed on tabular data moved from a main memory to the memories of a core processor, or to and from other memories. The internal memory of each data movement engine is private to the data movement engine.Type: GrantFiled: November 28, 2016Date of Patent: August 28, 2018Assignee: Oracle International CorporationInventors: David A. Brown, Sam Idicula, Erik Schlanger, Rishabh Jain, Michael Duller, Christopher Joseph Daniels, David Joseph Hawkins
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Patent number: 10061714Abstract: Techniques are described herein for efficient movement of data from a source memory to a destination memory. In an embodiment, in response to a particular memory location being pushed into a first register within a first register space, the first set of electronic circuits accesses a descriptor stored at the particular memory location. The descriptor indicates a width of a column of tabular data, a number of rows of tabular data, and one or more tabular data manipulation operations to perform on the column of tabular data. The descriptor also indicates a source memory location for accessing the tabular data and a destination memory location for storing data manipulation result from performing the one or more data manipulation operations on the tabular data.Type: GrantFiled: March 18, 2016Date of Patent: August 28, 2018Assignee: Oracle International CorporationInventors: David A. Brown, Rishabh Jain, Michael Duller, Sam Idicula, Erik Schlanger, David Joseph Hawkins
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Patent number: 10055358Abstract: Techniques are described herein for efficient movement of data from a source memory to a destination memory. In an embodiment, in response to a particular memory location being pushed into a first register within a first register space, the first set of electronic circuits accesses a descriptor stored at the particular memory location. The descriptor indicates a width of a column of tabular data, a number of rows of tabular data, and one or more tabular data manipulation operations to perform on the column of tabular data. The descriptor also indicates a source memory location for accessing the tabular data and a destination memory location for storing data manipulation result from performing the one or more data manipulation operations on the tabular data.Type: GrantFiled: March 18, 2016Date of Patent: August 21, 2018Assignee: Oracle International CorporationInventors: David A. Brown, Rishabh Jain, Sam Idicula, Erik Schlanger, David Joseph Hawkins
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Publication number: 20180225232Abstract: A memory controller comprises memory access circuitry configured to initiate a data access of data stored in a memory in response to a data access hint message received from another node in data communication with the memory controller; to access data stored in the memory in response to a data access request received from another node in data communication with the memory controller and to provide the accessed data as a data access response to the data access request.Type: ApplicationFiled: February 8, 2017Publication date: August 9, 2018Inventors: Michael FILIPPO, Jamshed JALAL, Klas Magnus BRUCE, Paul Gilbert MEYER, David Joseph HAWKINS, Phanindra Kumar MANNAVA, Joseph Michael PUSDESRIS
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Publication number: 20180150542Abstract: Techniques provide for hardware accelerated data movement between main memory and an on-chip data movement system that comprises multiple core processors that operate on the tabular data. The tabular data is moved to or from the scratch pad memories of the core processors. While the data is in-flight, the data may be manipulated by data manipulation operations. The data movement system includes multiple data movement engines, each dedicated to moving and transforming tabular data from main memory data to a subset of the core processors. Each data movement engine is coupled to an internal memory that stores data (e.g. a bit vector) that dictates how data manipulation operations are performed on tabular data moved from a main memory to the memories of a core processor, or to and from other memories. The internal memory of each data movement engine is private to the data movement engine.Type: ApplicationFiled: November 28, 2016Publication date: May 31, 2018Inventors: DAVID A. BROWN, SAM IDICULA, ERIK SCHLANGER, RISHABH JAIN, MICHAEL DULLER, CHRISTOPHER JOSEPH DANIELS, DAVID JOSEPH HAWKINS