Abstract: A method and apparatus for configuring multiple first programmable logic devices from a single memory includes a microprocessor, and a second programmable logic device containing the interface logic for the first programmable device and the microprocessor. The present invention allows multiple FPGAs to be programmed from a single memory structure under the control of the microprocessor thereby using fewer components than systems dedicating a separate memory to each FPGA. A communications port allows new configurations to be downloaded to the microprocessor memory. In addition, the present invention can be used in combination with standard systems with each FPGA having its own memory, with the microprocessor being able to select between the central microprocessor memory and the local memory for programming each FPGA.

Abstract: A method and system for bootstrapping a processor from a volatile memory device connected to the processor is disclosed. The first processor is bootstrapped from flash device. The reset lines of the second processor are asserted. The boot code for the second processor is loaded from the flash device into the volatile memory device. The reset lines of the second processor are de-asserted, wherein the processor then boots from the boot code stored in the volatile memory device. The same boot-strapping method can be extended to multi-drop systems where number of secondary processor can be more than one. A switchable means for the second processor to boot from volatile memory as described or from flash memory. A method also describes a mechanism to boot from synchronous volatile memory devices.

Abstract: A method and apparatus for configuring and determining the status of a first programmable logic devices includes a microprocessor, a second programmable logic device containing the interface logic for the first programmable device and the microprocessor, a status check that is linked to the second programmable logic device, the status check determines the condition of the first programmable logic device and a storage device linked to the microprocessor. A configuration code for the first programmable logic device is located on the storage device.

Abstract: A method and system for bootstrapping a processor from a volatile memory device connected to the processor is disclosed. The first processor is bootstrapped from flash device. The reset lines of the second processor are asserted. The boot code for the second processor is loaded from the flash device into the volatile memory device. The reset lines of the second processor are de-asserted, wherein the processor then boots from the boot code stored in the volatile memory device. The same boot strapping method can be extended to multi-drop systems where number of secondary processor can be more than one. A switchable means for the second processor to boot from volatile memory as described or from flash memory. A method also describes a mechanism to boot from synchronous volatile memory devices.

Abstract: A data transmission system transmits data from a first device to an interface device at a continuous rate and includes a first device for storing data and for transmitting data at a first data output rate. An interface device outputs data at a second data output rate different from the first data output rate. A preload buffer initially receives a predetermined amount of data from the first device and stores the initially received data. The preload buffer also transmits at least a portion of the initially received data at a third data output rate. The preload buffer receives additional data from the first device as the initially received data is transmitted from the preload buffer. A first buffer and a second buffer of generally equal size are sized to receive a single block of data from the preload buffer. The size of the single block of data is less than the predetermined amount of output data initially received and stored in the preload buffer.