Abstract: A method of formulating and packaging decision-making elements into a long constraint length Viterbi decoder which involves formulating the decision-making processors as individual Viterbi butterfly processors that are interconnected in a deBruijn graph configuration. A fully distributed architecture, which achieves high decoding speeds, is made feasible by novel wiring and partitioning of the state diagram. This partitioning defines universal modules, which can be used to build any size decoder, such that a large number of wires is contained inside each module, and a small number of wires is needed to connect modules. The total system is modular and hierarchical, and it implements a large proportion of the required wiring internally within modules and may include some external wiring to fully complete the deBruijn graph.

Abstract: A digital phase-lock loop (DPLL) which generates a signal with a phase that approximates the phase of a received signal with a linear estimator. The effect of a complication associated with non-zero transport delays related to DPLL mechanization is then compensated by a predictor. The estimator provides recursive estimates of phase, frequency, and higher order derivatives, while the predictor compensates for transport lag inherent in the loop.