Abstract: Disclosed is a method of analyzing an integrated-circuit system that is accurate for high frequency analysis and can predict problems at high frequencies that do not occur when the circuit is used at lower frequencies.

Abstract: A mode register is created during the design of a complex, multi-mode electronic circuit. The mode register may contain connections to various switches, clocks, multiplexers, or other portions of the circuit that may have settings necessary to operate the circuit in different modes. The mode register may be used during circuit simulation by setting the mode register to a certain setting when running a static timing analysis script or other type of circuit simulation. After the circuit design is completed and before manufacturing the circuit, the mode register is disabled or removed from the circuit.

Abstract: A mode register is created during the design of a complex, multi-mode electronic circuit. The mode register may contain connections to various switches, clocks, multiplexers, or other portions of the circuit that may have settings necessary to operate the circuit in different modes. The mode register may be used during circuit simulation by setting the mode register to a certain setting when running a static timing analysis script or other type of circuit simulation. After the circuit design is completed and before manufacturing the circuit, the mode register is disabled or removed from the circuit.

Abstract: An RTL back annotator for applying back annotated data to the RTL code of an RTL simulation for verifying actual timing performance for an ASIC array after layout during RTL simulation parses through annotation data from the back annotation file for the ASIC layout and generates RTL delays for each wire and register in the ASIC layout. The RTL annotator then applies the generated RTL delays to the RTL compiled design, thereby emulating the delays that a gate level netlist would have. In this manner, an RTL simulation having timings of the real layout may be run.