Abstract: A multi-stage resistive ladder network which uses extra stages to trim out resistance discrepencies. All of the stages are interconnected in a series. Nominally, current is divided in half within each stage. Half of the current is gated onto a bus in response to logic control signals, and the other half of the current is passed onto the next succeeding stage. Due to various processing limitations, the resistors comprising each stage vary slightly from their nominal value, which in turn upsets the current division. To compensate for this additional current dividing stages are serially connected to the last stage of the ladder. Current from these additional stages are selectively coupled onto the bus in response to the logic signals in addition to the current which is normally coupled thereto.

Abstract: A single chip integrated circuit analog-to-digital converter uses the successive approximation approach with resistor ladder-switching decoder digital-to-analog coverters coupled to a precision plural input comparator. An on board PROM is provided to store in digital form the information necessary to trim the digital-to-analog converters. The converter is actuated during wafer probing in the manufacturing process and the PROM is programmed with the trim information. Initially, the PROM is bypassed and the digital words needed for accurate trim applied externally. Once the correct trim words are found, the PROM is programmed with the correct words. A 13-bit converter is supplied with ten 7-bit trim words to achieve a fully trimmed product in wafer fabrication.

Abstract: A detector for application to integrated circuits useful in determining the alignment of a trimming laser. A metallization pattern is employed along with electrical detection circuitry to determine when the trimming laser becomes misaligned by a predetermined amount. The laser is precision aimed when the integrated circuit wafer is located in a step and repeat machine. As stepping continues the detector provides an indication when the cumulative error exceeds the predetermined value.

Abstract: A read only memory is fabricated using metal oxide semiconductor technology and is intended for incorporation into large scale integrated circuits. A plurality of memory transistors is arrayed in a configuration having columns, each of which is associated with an address line, and rows, each of which is associated with a word line. A memory transistor is located at each intersection of an address line and a word line. Each memory transistor represents a bit location and includes a severable conductive link coupled in series and located on top of the field oxide surrounding the memory transistors. Each memory transistor in a particular column has its gate coupled to an address line. Each memory transistor in a particular row completes a series circuit which includes the severable conductive link between a first power supply terminal and a word line. Each word line includes a resistor coupled to the other power supply terminal.

Abstract: A statistically enhanced ratio-matched network in a circuit chip is disclosed. The network may be either a resistance network or a capacitance network. In a ratio-matched resistance network, such as an R-2R resistance ladder, a plurality of resistances in a circuit chip have a rational ratio of resistance values to each other. All of the resistances each consists of an integral number of simultaneously fabricated resistors of approximately uniform dimensions, and certain critical resistances each consists of a series-parallel combination of the resistors for statistically enhancing the accuracy of the rational ratio of the critical resistances to each other.

Abstract: Two digital-to-analog converters are coupled in series across a reference potential source. Each converter includes a resistor ladder and switching tree that permits coupling the output to any single tap on the ladder. A digital word is split into two portions, each one of which operates one switching tree. The converters are weighted in accordance with the word bits applied. The switching tree outputs are combined to produce an analog output related to the reference potential and the digital word.

Abstract: A laser beam is employed to trim monolithic integrated circuits in wafer form in a step and repeat machine. The step and repeat action is adjusted to bring successive circuits on the wafer into trimming relationship with the laser. The circuit is measured and trimming accomplished to adjust the circuit performance to a precise specification. The step and repeat operation introduces a small error that accumulates as stepping proceeds. A laser beam error detector pattern is incorporated into the integrated circuit wafer and is designed to produce a response when the beam impingement error exceeds a predetermined value. The detector output causes the laser beam to be translated by an increment equal to the error and in the opposite direction. As a result, the laser beam aiming error is controlled by a known pattern rather than by an unknown cumulative error.