Abstract: An apparatus for linking a hot-plug device to a host includes a slave interface circuit for connection to the host; a master interface circuit for connection to the hot-plug device; and direction, data, and clock lines that link the master and slave interface circuits. A control logic circuit detects a Presence Detect signal on the direction line. A method of determining a connection between a host and a hot-plug device includes asserting a direction signal on a direction line to control a direction of a flow of data between the host and the hot-plug device; toggling the direction signal to indicate a presence of the hot-plug device; and indicating a disconnect after a given period of inactivity in the toggling. A method of linking a host and a hot-plug device interface circuit for connection to a hot-plug device includes asserting a Presence Detect signal on the direction line.

Abstract: An apparatus for linking a hot-plug device to a host includes a slave interface circuit for connection to the host; a master interface circuit for connection to the hot-plug device; and direction, data, and clock lines that link the master and slave interface circuits. A control logic circuit detects a Presence Detect signal on the direction line. A method of determining a connection between a host and a hot-plug device includes asserting a direction signal on a direction line to control a direction of a flow of data between the host and the hot-plug device; toggling the direction signal to indicate a presence of the hot-plug device; and indicating a disconnect after a given period of inactivity in the toggling. A method of linking a host and a hot-plug device interface circuit for connection to a hot-plug device includes asserting a Presence Detect signal on the direction line.

Abstract: A method for controlling hot-plug behavior includes identifying a hot-plug event caused by a hot-plug device; generating hot-plug threads that execute a hot-plug operation; executing a finite state machine state sequence to regulate hot-plug threads involved in the hot-plug operation; and completing the hot-plug operation at the end of the finite state machine state sequence. A computer usable medium has computer readable program code embodied therein for causing a computer system to execute the method for controlling hot-plug behavior. A hot-plug control system for a computer system includes a hot-plug device; a set of hot-plug threads that regulate operations in the hot-plug device; and a finite state machine that controls execution of instructions using the set of threads.

Abstract: A large multimaster I2C bus system is partitioned into smaller bus segments. The bus segments are connected by bridges that isolate the segments and direct selected transactions and commands between the segments. The bridge may handle bus segment error conditions and particularly a hang on the Port B bus by attempting to cause any device on the bus segment to respond after the bus bridge has attempted to acquire the segment for a first predetermined period of time. If the bus responds within the first predetermined period of time, the bus bridge resets the bus segment.

Abstract: A special bus master, called a configuration host, “walks” a bus system to discover the bus topology and bus bridges that form that topology. Once the bridges have been located, the configuration host assigns a bridge ID to each bridge and enters information into internal bridge registers that control the flow of information between bus segments. The configuration host also populates an address bitmap in each bridge in order to complete the bus system configuration. In one embodiment, the bus topology is a tree configuration and the configuration host performs a recursive procedure that configures each branch of the tree. During this configuration process the internal bridge registers and address bitmap in each bridge are populated.

Abstract: A switching apparatus provides an address extension for an environment, such as I2C, that uses devices with a limited address configurability. The switching apparatus provides connection between a main bus and one or more secondary busses to which additional devices are connected. The switching apparatus detects an address on the main bus, and determines whether it is intended for a device on a secondary bus. If so, it connects the main bus to the proper secondary bus where the device in question is located. It then translates the address to an address within the limited configurability of the devices, and places the translated address on the secondary bus where the addressed device is located.

Abstract: One or more bus bridges are used to partition a large I2C bus into smaller bus segments. By programming address bitmaps that are internal to each bridge, the various bus segments can be made to appear as one logical bus. In addition, the bus topology can be designed to maximize the ability to isolate faults within a given segment, thereby improving the ability of technicians to diagnose problems in very large I2C implementations. In one embodiment, the invention is a unidirectional bus bridge which is designed so that two such bridges can be used in parallel (facing in opposite directions) to implement a fully bi-directional bus bridge. In another embodiment, I2C slave addresses are replicated in a single logical I2C bus by addressing a tunnel command to a bridge, which command contains an address and causes the bridge to which it is addressed to forward the contained address.

Abstract: A special bus master, called a configuration host, “walks” a bus system to discover the bus topology and bus bridges that form that topology. Once the bridges have been located, the configuration host assigns a bridge ID to each bridge and enters information into internal bridge registers that control the flow of information between bus segments. The configuration host also populates an address bitmap in each bridge in order to complete the bus system configuration. In one embodiment, the bus topology is a tree configuration and the configuration host performs a recursive procedure that configures each branch of the tree. During this configuration process the internal bridge registers and address bitmap in each bridge are populated.

Abstract: A large multimaster I2C bus system is partitioned into smaller bus segments. The bus segments are connected by bridges that isolate the segments and direct selected transactions and commands between the segments. By programming address bitmaps that are internal to each bridge, transactions can pass through the bridges so that the various bus segments appear to be one logical bus. Because each bridge implements address filtering so that transactions are selectively forwarded from one side of the bridge to the other based on the contents of an internal address bitmap, I2C slave addresses can be arbitrarily populated on either side of the bridge. Duplicate I2C slave addresses can be also used on different segments of a single logical I2C bus system. Masters on one segment can reach devices connected to the same bus segment and can also reach devices with duplicate addresses on other bus segments by using a tunnel command addressed to a bridge.

Abstract: One or more bus bridges are used to partition a large I2C bus into smaller bus segments. By programming address bitmaps that are internal to each bridge, the various bus segments can be made to appear as one logical bus. In addition, the bus topology can be designed to maximize the ability to isolate faults within a given segment, thereby improving the ability of technicians to diagnose problems in very large I2C implementations. In one embodiment, the invention is a unidirectional bus bridge which is designed so that two such bridges can be used in parallel (facing in opposite directions) to implement a fully bidirectional bus bridge. In another embodiment, I2C slave addresses are replicated in a single logical I2C bus by addressing a tunnel command to a bridge, which command contains an address and causes the bridge to which it is addressed to forward the contained address.

Abstract: A switching apparatus provides an address extension for an environment, such as I2C, that uses devices with a limited address configurability. The switching apparatus provides connection between a main bus and one or more secondary busses to which additional devices are connected. The switching apparatus detects an address on the main bus, and determines whether it is intended for a device on a secondary bus. If so, it connects the main bus to the proper secondary bus where the device in question is located. It then translates the address to an address within the limited configurability of the devices, and places the translated address on the secondary bus where the addressed device is located.

Abstract: A “firewall” apparatus is placed between a single bus master device and a multimaster I2C bus system. The firewall apparatus transforms all multimaster bus errors into simple NAK errors and isolates the single bus master from the multimaster bus. Therefore the single bus master needs only to retry transactions that receive unexpected NAKs and all complex multimaster issues, such as bus collisions, transaction termination and bus recovery, associated with the actual error that occurred on the multimaster bus are handled by the firewall apparatus. In accordance with one embodiment, when the single bus master attempts to launch a transaction at a time when the multimaster I2C bus is busy, the firewall apparatus absorbs the address driven by the single bus master and then stalls the transaction until the firewall apparatus is able to successfully acquire and drive the address on the multimaster bus. The firewall apparatus is implemented in a preferred embodiment by a programmed microcontroller.

Abstract: In an electronic system with multiple power supplies, a method and apparatus dynamically determines the number of power supplies required to power up the system without overloading any supply. The individual power supplies do not turn on until the determined number of power supplies have received AC power and become operational before attempting a complete system power on. The amount of required power is determined before power up based on the actual power load present. The actual load is determined by sensing load indicators in each load device and computing the total power load. The amount of power from supplies which have received AC power is determined by detecting when AC power has been applied to each power supply and computing the total amount of power available. System power up is delayed when the number of power supplies which have received AC power is insufficient to power the system without an overload situation occurring.