Patents by Inventor Joseph J. Fabula

Joseph J. Fabula has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Identifying an atomic element using an integrated circuit
    Patent number: 8476601
    Abstract: Systems and methods are provided for identifying an atomic element in proximity to an integrated circuit. Trace amounts of a contaminant are identifiable. The atomic element is exposed to neutron radiation to convert a portion of the atomic element into a radioactive isotope of the atomic element. Upsets are measured for the binary states of the memory cells of the integrated circuit during a time period following the exposure to the neutron radiation. The atomic element is identified from the upsets of the binary states of the memory cells of the integrated circuit.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: July 2, 2013
    Assignee: Xilinx, Inc.
    Inventors: Joseph J. Fabula, Austin H. Lesea, Raymond J. Matteis
  • Single event upset in SRAM cells in FPGAs with high resistivity gate structures
    Patent number: 7452765
    Abstract: SEU-hardening series resistances loads are formed within the gate structures of cross-coupled inverters of a latch. For some embodiments, the gate contact for the input of each cross-coupled inverter has a sufficiently high resistance to provide the SEU-hardening series resistance. For other embodiments, a conductive trace layer coupled to the input of each cross-coupled inverter includes a high-resistivity portion that provides the SEU-hardening series resistance.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: November 18, 2008
    Assignee: XILINX, Inc.
    Inventors: Martin L. Voogel, Austin H. Lesea, Joseph J. Fabula, Carl H. Carmichael, Shahin Toutounchi, Michael J. Hart, Steven P. Young, Kevin T. Look, Jan L. de Jong
  • Single event upset in SRAM cells in FPGAs with high resistivity gate structures
    Patent number: 6982451
    Abstract: SEU-hardening series resistances loads are formed within the gate structures of cross-coupled inverters of a latch. For some embodiments, the gate contact for the input of each cross-coupled inverter has a sufficiently high resistance to provide the SEU-hardening series resistance. For other embodiments, a conductive trace layer coupled to the input of each cross-coupled inverter includes a high-resistivity portion that provides the SEU-hardening series resistance.
    Type: Grant
    Filed: March 27, 2003
    Date of Patent: January 3, 2006
    Assignee: Xilinx, Inc.
    Inventors: Martin L. Voogel, Austin H. Lesea, Joseph J. Fabula, Carl H. Carmichael, Shahin Toutounchi, Michael J. Hart, Steven P. Young, Kevin T. Look, Jan L. de Jong
  • Low leakage N-channel SOS transistors and method of making them
    Patent number: 4252574
    Abstract: A method for making low leakage N-channel silicon-on-sapphire (SOS) transistor is described. The transistor has reduced edge leakage as a result of acceptor ion impurities introduced into the edges of the silicon islands on which the transistor is formed. The acceptor impurities are introduced into the epitaxial silicon layer immediately before etching the layer to produce the islands. The impurities are then diffused under the edge of the masking layer prior to the removal of the portions of the silicon epitaxial layer, and leaving the edges of the islands more heavily doped than the surface of the island.
    Type: Grant
    Filed: November 9, 1979
    Date of Patent: February 24, 1981
    Assignee: RCA Corporation
    Inventor: Joseph J. Fabula
  • Process for manufacturing a radiation hardened oxide
    Patent number: 4139658
    Abstract: A pyrogenic oxide is grown on a silicon wafer in a furnace by oxidizing hydrogen in the presence of an excess amount of oxygen as well as anhydrous hydrogen chloride to produce steam within the furnace. After growing a suitable pyrogenic oxide layer, the hydrogen and hydrogen chloride flows are turned off while the oxygen flow is continued to grow a dry oxide. A nitrogen anneal while the wafer is slowly pulled from the furnace completes the hybrid, radiation hard oxide layer.
    Type: Grant
    Filed: June 23, 1976
    Date of Patent: February 13, 1979
    Assignee: RCA Corp.
    Inventors: Seymour H. Cohen, Joseph J. Fabula