Abstract: Hierarchical semiconductor structure design is disclosed. One aspect of the invention is a computerized system that includes a semiconductor structure (such as a semiconductor test structure) and a basic atom. The system also includes a hierarchy of abstractions ordered from highest to lowest. Each abstraction relates a plurality of instances of an immediately lower abstraction; the highest abstraction corresponds to the structure, and the lowest abstraction corresponds to the basic atom. A plurality of sets of parameters also is included within the system, where each set of parameters corresponds to an instance of an abstraction. Changing one of the set of parameters for an instance changes at least one of the set of parameters for an instance of an immediately lower abstraction.

Abstract: Parameter population of cells for a hierarchical semiconductor structure via file relation is disclosed. One aspect of the invention is a computerized system that includes a global file of global variables, a plurality of local files, and a plurality of cells. Each local file relates a plurality of local variables to the global variables. Each cell corresponds to a local file and has a set of parameters corresponding to the local variables of the local file.

Abstract: Hierarchical semiconductor structure design is disclosed. One aspect of the invention is a computerized system that includes a semiconductor structure (such as a semiconductor test structure) and a basic atom. The system also includes a hierarchy of abstractions ordered from highest to lowest. Each abstraction relates a plurality of instances of an immediately lower abstraction; the highest abstraction corresponds to the structure, and the lowest abstraction corresponds to the basic atom. A plurality of sets of parameters also is included within the system, where each set of parameters corresponds to an instance of an abstraction. Changing one of the set of parameters for an instance changes at least one of the set of parameters for an instance of an immediately lower abstraction.

Abstract: Hierarchical semiconductor structure design is disclosed. One aspect of the invention is a computerized system that includes a semiconductor structure (such as a semiconductor test structure) and a basic atom. The system also includes a hierarchy of abstractions ordered from highest to lowest. Each abstraction relates a plurality of instances of an immediately lower abstraction; the highest abstraction corresponds to the structure, and the lowest abstraction corresponds to the basic atom. A plurality of sets of parameters also is included within the system, where each set of parameters corresponds to an instance of an abstraction. Changing one of the set of parameters for an instance changes at least one of the set of parameters for an instance of an immediately lower abstraction.

Abstract: Hierarchical semiconductor structure design is disclosed. One aspect of the invention is a computerized system that includes a semiconductor structure (such as a semiconductor test structure) and a basic atom. The system also includes a hierarchy of abstractions ordered from highest to lowest. Each abstraction relates a plurality of instances of an immediately lower abstraction; the highest abstraction corresponds to the structure, and the lowest abstraction corresponds to the basic atom. A plurality of sets of parameters also is included within the system, where each set of parameters corresponds to an instance of an abstraction. Changing one of the set of parameters for an instance changes at least one of the set of parameters for an instance of an immediately lower abstraction.

Abstract: Parameter population of cells for a hierarchical semiconductor structure via file relation is disclosed. One aspect of the invention is a computerized system that includes a global file of global variables, a plurality of local files, and a plurality of cells. Each local file relates a plurality of local variables to the global variables. Each cell corresponds to a local file and has a set of parameters corresponding to the local variables of the local file.

Abstract: A technique for forming high-value, inter-nodal, polysilicon coupling resistors using self-aligned silicidation and local interconnect in a double polysilicon process. In an SRAM memory, the technique may be utilized to interconnect the gates of each CMOS invertor to created radiation-hardened cells. Process flow is conventional through gate formation, with transistor gates being patterned from a first polysilicon (poly-1) layer. The transistors which will form each invertor are constructed on distinct active areas. The gate of each invertor transistor extends beyond an edge of the field oxide region, such that an end portion of each gate is superjacent different portions of a single field oxide region. These gate end portions are separated by an expanse of exposed field oxide. The process then departs from convention with a blanket silicon nitride deposition, followed by blanket deposition of a second polysilicon (poly-2) layer.

Abstract: This invention constitutes a 10-12 mask, split-polysilicon process for fabricating dynamic random access memories of the stacked capacitor type for the one-megabit generation and beyond.

Abstract: A process for creating two thicknesses or gate oxide within a dynamic random memory. The process begins by thermally growing a first layer of gate oxide on a silicon substrate. This first layer is then masked with photoresist in regions where cell access transistors will ultimately be fabricated. All oxide that is not masked is then removed with an oxide etch. After the photoresist is stripped, a second layer of gate oxide is thermally grown on the substrate. The resultant oxided layer, which comprises multiple-thickness components, is used as a pad oxide layer during a conventional LOCOS operation. Peripheral driver transistors are construction on top of a thin layer of gate oxide so as to optimize their performance, whereas, cell access transistors are constructed on top of a thicker layer of gate oxide so as to minimize row line capacitance. A net increase in row line access speed is thus obtained.

Abstract: A split-polysilicon CMOS DRAM process incorporating selective, self-aligned silicidation of conductive regions and silicon nitride blanket protection of N-channel regions during the etch steps which create P-channel transistor gate spacers, thus avoiding transistor breakdown voltage problems associated with the double etching of the N-channel regions that was heretofore required for the creation of LDD-type P-channel transistors and self-aligned silicidation of conductive regions utilizing a split-polysilicon CMOS process. A CVD anti-silicidation oxide layer and a protective silicon nitride layer are blanket deposited on top of all circuitry following the patterning of the cell plate. The protective nitride layer protects the N-channel regions during the etches used to create the P-channel channel transistor gate spacers. Following the stripping of the protective nitride layer, an optional antisilicidation thermal oxide layer may be grown on the P-channel substrate.

Abstract: A split-polysilicon CMOS DRAM process incorporating self-aligned silicidation of the cell plate, transistor gates and N+ regions with a minimum of additional processing steps. By employing a light oxidation step to protect the P-channel transistor sidewall gates from silicidation during a subsequent processing step, the process avoids the problems that may be created by the double etching of the field oxide and active area regions that has heretofore been required for self-aligned silidation utilizing a split-polysilicon CMOS process. A protective nitride layer is used to prevent oxidation on those regions which are to be silicided. When this improved process is utilized for DRAM fabrication, the protective nitride layer may also be utilized as the cell dielectric.