Patents by Inventor Joseph J. Oler, Jr.
Joseph J. Oler, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9255962Abstract: Embodiments of the present invention disclose an apparatus and method to determine the intra-chip variation of an integrated circuit. In an embodiment, an apparatus comprises a test macro that includes two or more test structures; wherein each test structure includes identical copies of the same performance monitor; wherein each performance monitor has a unique bounding circuitry that encompasses the performance monitor; and wherein the two or more test structures are positioned close enough to each other as to reduce systematic across chip variation between the two or more test structures.Type: GrantFiled: August 15, 2013Date of Patent: February 9, 2016Assignee: GlobalFoundries, Inc.Inventors: Jeanne P. S. Bickford, Aurelius L. Graninger, Christopher T. McEvoy, Joseph J. Oler, Jr.
-
Patent number: 8966431Abstract: Approaches are provided for improving timing of new and existing semiconductor products. Specifically, a method is provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to set starting across chip variation assumptions using design rules. The programming instructions are further operable to design a test chip and/or product chip using the starting across chip variation assumptions to close timing of the design. The programming instructions are further operable to place devices in the test chip and/or product chip. The programming instructions are further operable to compare performance of the devices within the test chip and/or the product chip to the starting across chip variation assumptions. The programming instructions are further operable to adjust the starting across chip variation assumptions based on the measured performance of the test chip and/or the product chip.Type: GrantFiled: November 21, 2012Date of Patent: February 24, 2015Assignee: International Business Machines CorporationInventors: Jeanne P. Bickford, Howard B. Druckerman, Erik L. Hedberg, Joseph J. Oler, Jr.
-
Publication number: 20150048860Abstract: Embodiments of the present invention disclose an apparatus and method to determine the intra-chip variation of an integrated circuit. In an embodiment, an apparatus comprises a test macro that includes two or more test structures; wherein each test structure includes identical copies of the same performance monitor; wherein each performance monitor has a unique bounding circuitry that encompasses the performance monitor; and wherein the two or more test structures are positioned close enough to each other as to reduce systematic across chip variation between the two or more test structures.Type: ApplicationFiled: August 15, 2013Publication date: February 19, 2015Applicant: International Business Machines CorporationInventors: Jeanne P.S. Bickford, Aurelius L. Graninger, Christopher T. McEvoy, Joseph J. Oler, JR.
-
Publication number: 20140143748Abstract: Approaches are provided for improving timing of new and existing semiconductor products. Specifically, a method is provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to set starting across chip variation assumptions using design rules. The programming instructions are further operable to design a test chip and/or product chip using the starting across chip variation assumptions to close timing of the design. The programming instructions are further operable to place devices in the test chip and/or product chip. The programming instructions are further operable to compare performance of the devices within the test chip and/or the product chip to the starting across chip variation assumptions. The programming instructions are further operable to adjust the starting across chip variation assumptions based on the measured performance of the test chip and/or the product chip.Type: ApplicationFiled: November 21, 2012Publication date: May 22, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jeanne P. BICKFORD, Howard B. DRUCKERMAN, Erik L. HEDBERG, Joseph J. OLER, JR.
-
Patent number: 8095902Abstract: A design structure for a computer-aided design system for generating a functional design model of an integrated circuit design (having nets comprising wires) determines critical parameters for coupling noise between the wires of the nets and acceptable limits for the critical parameters. Further, methods herein include designing a ring oscillator to have stages, each of the stages measuring only one of the critical parameters. This ring oscillator is then included within an integrated circuit design and associated design structure. The embodiments herein produce an integrated circuit according to this integrated circuit design and operate the ring oscillator within the integrated circuit to measure the critical parameters of the integrated circuit and produce test results. These test results are output to determine whether the test results are within the acceptable limits.Type: GrantFiled: August 18, 2008Date of Patent: January 10, 2012Assignee: International Business Machines CorporationInventors: Anthony W. Fazekas, Kenneth Mon Ngai, Joseph J. Oler, Jr.
-
Patent number: 7958471Abstract: A design structure for a computer-aided design system for generating a functional design model of an integrated circuit design (having nets comprising wires) determines critical parameters for coupling noise between the wires of the nets and acceptable limits for the critical parameters. Further, methods herein include designing a ring oscillator to have stages, each of the stages measuring only one of the critical parameters. This ring oscillator is then included within an integrated circuit design and associated design structure. The embodiments herein produce an integrated circuit according to this integrated circuit design and operate the ring oscillator within the integrated circuit to measure the critical parameters of the integrated circuit and produce test results. These test results are output to determine whether the test results are within the acceptable limits.Type: GrantFiled: August 18, 2008Date of Patent: June 7, 2011Assignee: International Business Machines CorporationInventors: Anthony W. Fazekas, Kenneth Mon Ngai, Joseph J. Oler, Jr.
-
Publication number: 20100042962Abstract: A design structure for a computer-aided design system for generating a functional design model of an integrated circuit design (having nets comprising wires) determines critical parameters for coupling noise between the wires of the nets and acceptable limits for the critical parameters. Further, methods herein include designing a ring oscillator to have stages, each of the stages measuring only one of the critical parameters. This ring oscillator is then included within an integrated circuit design and associated design structure. The embodiments herein produce an integrated circuit according to this integrated circuit design and operate the ring oscillator within the integrated circuit to measure the critical parameters of the integrated circuit and produce test results. These test results are output to determine whether the test results are within the acceptable limits.Type: ApplicationFiled: August 18, 2008Publication date: February 18, 2010Inventors: Anthony W. Fazekas, Kenneth Mon Ngai, Joseph J. Oler, JR.
-
Publication number: 20100042960Abstract: A design structure for a computer-aided design system for generating a functional design model of an integrated circuit design (having nets comprising wires) determines critical parameters for coupling noise between the wires of the nets and acceptable limits for the critical parameters. Further, methods herein include designing a ring oscillator to have stages, each of the stages measuring only one of the critical parameters. This ring oscillator is then included within an integrated circuit design and associated design structure. The embodiments herein produce an integrated circuit according to this integrated circuit design and operate the ring oscillator within the integrated circuit to measure the critical parameters of the integrated circuit and produce test results. These test results are output to determine whether the test results are within the acceptable limits.Type: ApplicationFiled: August 18, 2008Publication date: February 18, 2010Inventors: Anthony W. Fazekas, Kenneth Mon Ngai, Joseph J. Oler, JR.