Abstract: One embodiment of the present invention provides an apparatus that flexibly allocates I/O pins used for bus grant signals between bus controllers. The apparatus includes a semiconductor chip containing a first bus arbitration circuit and a second bus arbitration circuit. A first set of grant lines originates from the first bus arbitration circuit and is used to grant control of a first bus to devices on the first bus. This first set of grant lines is divided into a first subset of grant lines and a second subset of grant lines. A second set of grant lines originates from the second bus arbitration circuit and is used to grant control of a second bus to devices on the second bus. This second set of grant lines is divided into a third subset of grant lines and a fourth subset of grant lines. A selector circuit selects a plurality of outputs from between the first subset of grant lines and the third subset of grant lines.

Abstract: One embodiment of the present invention provides a method for flexibly allocating I/O pins used for bus grant signals between bus controllers located on a semiconductor chip. The method operates by receiving a first set of grant lines from a first bus arbitration circuit. This first set of grant lines is used to grant control of a first bus to devices on the first bus. The method divides the first set of grant lines into a first subset of grant lines and a second subset of grant lines. The method also receives a second set of grant lines from a second bus arbitration circuit. This second set of grant lines is used to grant control of a second bus to devices on the second bus. The method divides the second set of grant lines into a third subset of grant lines and a fourth subset of grant lines. Next, the method selects outputs from between the first subset of grant lines and the third subset of grant lines, and drives the outputs off of the semiconductor chip through a first set of output pins.

Abstract: A bus arbitration regulates access to a common bus by a plurality of devices by assigning each device a priority rank. A current weighted bandwidth of each device is set equal to a desired weighted bandwidth. A request to access the common bus is granted to the device having the highest priority rank among a set of requesting devices. The current weighted bandwidth the first device is decremented. The priority rank of the serviced device is set equal to a lowest value if its current weighted bandwidth is equal to a minimum value. The priority rank of a set of devices which previously had a lower priority rank than the first device is increased. The current weighted bandwidth of the serviced device is set equal to the desired weighted bandwidth. After a number of bus transactions have been completed, the desired weighted bandwidth of the devices may be adjusted to based upon system performance.

Abstract: A computer system stores data according to a plurality of different error handling schemes. The computer system includes a memory controller with a plurality of different error handling modules, each of which can be selectively associated with one or more memory blocks. Each of the error handling modules is structured to write data to and read data from its associated memory block according to a different error handling scheme. A memory controller includes a separate configuration register for each of the plurality of memory blocks. Each configuration register stores an indication of the error handling module that will be employed to write data to and read data from the memory block associated with the configuration register.

Abstract: A method for processing multiple memory requests in a pipeline. Each memory request is processed in part by a plurality of stages. In a first stage, the memory request is decoded. In a second stage, the address information for the memory request is processed. In a third stage, the data for the memory request is transferred. A request buffer is used to hold each of the memory requests during the processing of each of the memory requests.

Abstract: A bus arbitration regulates access to a common bus by a plurality of devices by assigning each device a priority rank. A current weighted bandwidth of each device is set equal to a desired weighted bandwidth. A request to access the common bus is granted to the device having the highest priority rank among a set of requesting devices. The current weighted bandwidth the first device is decremented. The priority rank of the serviced device is set equal to a lowest value if its current weighted bandwidth is equal to a minimum value. The priority rank of a set of devices which previously had a lower priority rank than the first device is increased. The current weighted bandwidth of the serviced device is set equal to the desired weighted bandwidth. After a number of bus transactions have been completed, the desired weighted bandwidth of the devices may be adjusted to based upon system performance.

Abstract: A memory controller which has multiple stages of pipelining. A request buffer is used to hold the memory request from the processor and peripheral devices. The request buffer comprises a set of rotational registers that holds the address, the type of transfer and the count for each request. The pipeline includes a decode stage, a memory address stage, and a data transfer stage. Each stage of the pipeline has a pointer to the request buffer. As each stage completes its processing, a state machine updates the pointer for each of the stages to reference a new memory request which needs to be processed.

Abstract: A method for processing multiple memory requests in a pipeline. Each memory request is processed in part by a plurality of stages. In a first stage, the memory request is decoded. In a second stage, the address information for the memory request is processed. In a third stage, the data for the memory request is transferred. A request buffer is used to hold each of the memory requests during the processing of each of the memory requests.

Abstract: A memory controller which has multiple stages of pipelining. A request buffer is used to hold the memory request from the processor and peripheral devices. The request buffer comprises a set of rotational registers that holds the address, the type of transfer and the count for each request. The pipeline includes a decode stage, a memory address stage, and a data transfer stage. Each stage of the pipeline has a pointer to the request buffer. As each stage completes its processing, a state machine updates the pointer for each of the stages to reference a new memory request which needs to be processed.

Abstract: An architecture for storing, addressing and retrieving graphics data from one of multiple memory controllers. In a first embodiment of the invention, one of the memory controllers having an accelerated graphics port (AGP) includes a set of registers defining a range of addresses handled by the memory controller that are preferably to be used for all AGP transactions. The AGP uses a graphics address remapping table (GART) for mapping memory. The GART includes page table entries having translation information to remap virtual addresses falling within the GART range to their corresponding physical addresses. In a second embodiment of the invention, a plurality of the memory controllers have an AGP, wherein each of the plurality of the memory controllers supplies a set of registers defining a range of addresses that is preferably used for AGP transactions.

Abstract: A method of operating a computer system having first and second random access memory (RAM) modules for storing digital information, and first and second system controllers coupled to the first and second RAM modules, respectively. The first system controller has a first address decoder that allocates to the first RAM module a first set of addresses. The second system controller has a second address decoder that allocates to the second RAM module a second set of addresses. By employing two system controllers to control two RAM modules, a computer system can execute two memory transactions simultaneously and can eliminate or reduce the number of memory access delays incurred. The computer system can allocate addresses according to various interleaving schemes, such as page interleaving, cache line interleaving and word interleaving. A configuration register can be employed to allow programming to select which of the interleaving schemes to employ.

Abstract: An architecture for storing, addressing and retrieving graphics data from one of multiple memory controllers. In a first embodiment of the invention, one of the memory controllers having an accelerated graphics port (AGP) includes a set of registers defining a range of addresses handled by the memory controller that are preferably to be used for all AGP transactions. The AGP uses a graphics address remapping table (GART) for mapping memory. The GART includes page table entries having translation information to remap virtual addresses falling within the GART range to their corresponding physical addresses. In a second embodiment of the invention, a plurality of the memory controllers have an AGP, wherein each of the plurality of the memory controllers supplies a set of registers defining a range of addresses that is preferably used for AGP transactions.

Abstract: A computer system stores data according to a plurality of different error handling schemes. The computer system includes a memory controller with a plurality of different error handling modules, each of which can be selectively associated with one or more memory blocks. Each of the error handling modules is structured to write data to and read data from its associated memory block according to a different error handling scheme. A memory controller includes a separate configuration register for each of the plurality of memory blocks. Each configuration register stores an indication of the error handling module that will be employed to write data to and read data from the memory block associated with the configuration register.

Abstract: A memory fault correction system enables plural data bit errors in a single data word to be corrected in an efficient manner. The system divides each data word into a plurality of sub-words and creates a separate error correction code for each of the sub-words. Each of the error correction codes includes a plurality of check bits with check bit values based on the data bit values of the corresponding sub-word of the data word. The computer system includes a plurality of error correction modules each performing error correction on a separate sub-word of the data word. A memory controller rearranges the data bits of the data word when forming the sub-words such that consecutive data bits are arranged in separate sub-words.

Abstract: A computer system includes a memory requester that interfaces with a memory module that includes memory portions. An error map that identifies the defective memory portions of the memory module is created and stored in the computer system. Using the error map, a remapping table that maps each of the defective memory portions to a non-defective memory portion in the memory module is created and then stored. In response to receiving from the memory requester a request for access to a requested memory portion of the memory module, a determination is made from the error map whether the requested memory portion is one of the defective memory portions. If the error map indicates that the requested memory portion is one of the defective memory portions, then a determination is made from the remapping table the non-defective memory portion to which the requested memory portion is mapped.

Abstract: A computer system has first and second random access memory (RAM) modules for storing digital information, and first and second system controllers coupled to the first and second RAM modules, respectively. The first system controller has a first address decoder that allocates to the first RAM module a first set of addresses. The second system controller has a second address decoder that allocates to the second RAM module a second set of addresses. By employing two system controllers to control two RAM modules, a computer system can execute two memory transactions simultaneously and can eliminate or reduce the number of memory access delays incurred. The computer system can allocate addresses according to various interleaving schemes, such as page interleaving, cache line interleaving and word interleaving for different memory segments. A configuration register can be employed to allow programming to select which of the interleaving schemes to employ.

Abstract: A computer system includes a memory controller that interfaces a memory requester with a memory device that may include defective memory cells. For each of plural memory blocks, defective bit sets having one or more defective memory cells are identified. A bit set error map is created and stored which identifies the defective bit sets of each of the memory blocks. In response to receiving from the memory requester a request for access to a requested storage location of the memory device, a determination is made from the error map whether the storage location is in a memory block that includes one or more defective bit sets. If the error map indicates that the requested storage location is in a memory block with one or more defective bit sets, then a determination is made from the error map which of the bit sets are defective. To execute the memory access request, the memory controller accesses the non-defective bit sets to which the detective bit sets have been mapped.

Abstract: A computer system has a system memory, cache memory, system controller that process memory transactions. The system controller transmits a memory request to the system memory without waiting for the cache memory to be snooped to determine whether the cache memory stores information in an address corresponding to a selected address of the system memory. The system controller may transmit a snoop request to the cache memory concurrently with or after the memory request is transmitted to the system memory. The system controller may have a control switch that uses a first pathway for the memory request and a second pathway for the snoop request so that the snoop and memory requests can be transmitted simultaneously.

Abstract: A method processes memory transactions in a computer system having a system memory and a cache memory. The method transmits a memory request to the system memory without waiting for the cache memory to be snooped to determine whether the cache memory stores information in an address corresponding to a selected address of the system memory. The method may transmit a snoop request to the cache memory concurrently with or after the memory request is transmitted to the system memory. The method may be implemented using a system controller having a control switch that uses a first pathway for the memory request and a second pathway for the snoop request so that the snoop and memory requests can be transmitted simultaneously.

Abstract: A computer system includes a memory controller that interfaces a memory requester with a memory device that may include defective memory cells. For each of plural memory blocks, defective bit sets having one or more defective memory cells are identified. A bit set error map is created and stored which identifies the defective bit sets of each of the memory blocks. In response to receiving from the memory requester a request for access to a requested storage location of the memory device, a determination is made from the error map whether the storage location is in a memory block that includes one or more defective bit sets. If the error map indicates that the requested storage location is in a memory block with one or more defective bit sets, then a determination is made from the error map which of the bit sets are defective. To execute the memory access request, the memory controller accesses the non-defective bit sets to which the defective bit sets have been mapped.